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b7
b6
b5
b4
b3
b2
(b15)
b7
Fig. 6.4.1 Structures of timer Bi mode register and timer Bi register in event counter mode
b1
b0
0 1
Timer Bi mode register (i = 0 to 2) (Addresses 5B
Bit
Operating mode select bits
0
1
Count polarity select bit
2
3
Nothing is assigned.
4
This bit is ignored in event counter mode.
5
These bits are ignored in event counter mode.
6
7
(b8)
b0
b7
7751 Group User's Manual
Bit name
b1 b0
0 1 : Event counter mode
b3 b2
0 0 : Count at falling edge of external signal
0 1 : Count at rising edge of external signal
1 0 : Counts at both falling and rising edges
of external signal
1 1 : Not selected
b0
Timer B0 register (Addresses 51
Timer B1 register (Addresses 53
Timer B2 register (Addresses 55
Bit
15 to 0
These bits can be set to "0000
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
TIMER B
6.4 Event counter mode
to 5D
)
16
16
Functions
, 50
)
16
16
, 52
)
16
16
, 54
)
16
16
Functions
" to "FFFF
."
16
16
At reset
RW
0
RW
0
RW
0
RW
0
RW
—
Undefined
—
Undefined
0
RW
0
RW
At reset
RW
RW
Undefined
6–15
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