Operation Clock For Internal Peripheral Devices - Renesas 7700 FAMILY User Manual

14.2.2 Operation clock for internal peripheral devices

The operation clock for the internal peripheral devices uses φ or φ divided by 2 as its clock source.
The clock source of the operation clock for internal peripheral devices is selected by the clock source for
peripheral devices select bit (bit 2 at address 5F
Figure 14.2.2 shows the structure of processor mode register 1 (address 5F
When f(X ) > 25 MHz, fix the clock source for peripheral devices select bit to "0."
IN
b7 b6 b5 b4 b3 b2
0 0
Fig. 14.2.2 Structure of processor mode register 1
CLOCK GENERATING CIRCUIT
b1 b0
Processor mode register 1 (Address 5F
0 0
Bit
1, 0
Fix these bits to "0."
Clock source for peripheral
2
devices select bit
CPU running speed select bit
3
Bus cycle select bits
4
5
Fix these bits to "0."
7, 6
Note: Fix this bit to "0" when f(X
: Bits 0, 1, and bits 3 to 7 are not used for the clock generating circuit.
7751 Group User's Manual
).
16
)
16
Bit name
0 : divided by 2
(Note)
1 :
0 : High-speed running
1 : Low-speed running
(Note)
In high-speed running
b5 b4
0 0 : 5 access in high-speed running
0 1 : 4 access in high-speed running
1 0 : 3 access in high-speed running
1 1 : Not selected
In low-speed running
b5 b4
0 0 : Not selected
0 1 : 4 access in low-speed running
1 0 : 3 access in low-speed running
1 1 : 2 access in low-speed running
) > 25 MHz.
IN
14.2 Clock
).
16
Functions
At reset
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
14–5