Interrupt Control Register - Renesas 7700 FAMILY User Manual

Interrupt control register

b7 b6 b5 b4 b3 b2
b7 b6 b5 b4 b3 b2
b1 b0
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 70
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit
3
7 to 4
Nothing is assigned.
Note: The A-D conversion interrupt request bit becomes undefined after reset.
b1 b0
INT to INT interrupt control registers (Addresses 7D
0 2
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit (Note)
3
4 Polarity select bit
Level sense/Edge sense select bit
5
Nothing is assigned.
7, 6
Note: The INT
7751 Group User's Manual
to 7C
16
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
0 : Set the interrupt request bit at
1 : Set the interrupt request bit at
0 : Edge sense
1 : Level sense
to INT interrupt request bits are invalid when selecting the level sense.
0 2
APPENDIX
Appendix 3. Control registers
)
16
Functions
Low level
High level
to 7F )
16 16
Functions
Low level
High level
"H" level for level sense and at
falling edge for edge sense.
"L" level for level sense and at
rising edge for edge sense.
RW
At reset
0 RW
0 RW
0 RW
0
RW
(Note)
–
Undefined
At reset RW
RW
0
0 RW
0
RW
0 RW
0 RW
0
RW
–
Undefined
20–31