Table of Contents
Advertisement
Read command
Figure 19.2.2 shows the read command execution timing.
The command code "00
The low–order 8 bits and the high–order 8 bits are input at the second and third transfer.
When setting "L" level to the OE signal, the data of the specified address (input address) is read
out and latched up to the internal data latch.
When returning "H" level to the OE signal and inputting the serial clock, the data which is latched
up to the data latch is output externally.
SCLK
SDA
0 0 0 0 0 0 0 0
Command code input(00
OE
BUSY
"L"
Note: When outputting the read data, the SDA pin is switched for output at the first falling edge of the serial clock.
The SDA pin is placed in the floating state during the t
(at the 8th bit).
Fig. 19.2.2 Read command execution timing
FLASH MEMORY VERSION
" is input at the first transfer.
16
___
___
t
t
CH
CH
A
A
7
0
)
Read address input
16
(Low-order)
7751 Group User's Manual
19.2 Serial input/output mode
A
A
8
1
5
Read address input
(High-order)
t
t
CR
Read
period after the last rising edge of the serial clock
h(C-E)
D
0
Read data output
(Note)
t
WR
RC
D
7
19–25
Advertisement
Table of Contents
