Renesas 7700 FAMILY User Manual page 336

15.10 Memory expansion mode and microprocessor mode : When 4- φ access in low-speed running
Switching characteristics (V
Symbol
t Port P4 data output delay time
d(E–P4Q)
t Port P5 data output delay time
d(E–P5Q)
t Port P6 data output delay time
d(E–P6Q)
t Port P7 data output delay time
d(E–P7Q)
t Port P8 data output delay time
d(E–P8Q)
φ high-level pulse width
t
w( φ H)
φ low-level pulse width
t
w( φ L)
φ
t
d(E– φ
output delay time
)
1 1
_
t
E low-level pulse width
w(EL)
t
Port P0 address output delay time
d(P0A–E)
Port P1 data output delay time (BYTE = "L")
t
d(E–P1Q)
t Port P1 floating start delay time (BYTE = "L")
pxz(E–P1Z)
t
d(P1A–E) Port P1 address output delay time
Port P1 address output delay time
t
d(P1A–ALE)
t
Port P2 data output delay time
d(E–P2Q)
t
Port P2 floating start delay time
pxz(E–P2Z)
Port P2 address output delay time
t
d(P2A–E)
t
Port P2 address output delay time
d(P2A–ALE)
t
ALE output delay time
d(E–ALE)
t
ALE output delay time
d(ALE–E)
t
ALE pulse width
w(ALE)
____
t
BHE
d(BHE–E)
__
t
R/W
d(R/W–E)
Note: For test conditions, refer to Figure 15.15.1.
ELECTRICAL CHARACTERISTICS
= 5 V±10%, V
CC
Parameter
output delay time
output delay time
7751 Group User's Manual
= 0 V, Ta = –20 to 85 °C, f(X
SS
) = 25 MHz, unless otherwise noted)
IN
Limits
Data formula
(Min.)
Min.
1 10 9
– 20
20
f(X )
IN
9
1 10
– 20 20
f(X )
IN
0
9
4 10
135
– 25
f(X )
IN
3 10 9
– 28
92
f(X )
IN
3 10 9
– 28
92
f(X )
IN
9
2 10
– 28 52
f(X )
IN
3 10 9
– 28
92
f(X )
IN
2 10 9
– 28
52
f(X )
IN
1 10 9
– 20
20
f(X )
IN
4
2 10 9
– 18
62
f(X )
IN
9
3 10
– 20
100
f(X )
IN
3 10 9
– 20
100
f(X )
IN
Unit
Max.
60 ns
60 ns
60
ns
60 ns
ns
60
ns
ns
18 ns
ns
ns
ns
35
5 ns
ns
ns
35 ns
5
ns
ns
ns
ns
ns
ns
ns
ns
15–29