Renesas 7700 FAMILY User Manual page 277

CONNECTION WITH EXTERNAL DEVICES
12.2 Bus cycle
b7 b6 b5 b4 b3 b2
0 0
Fig. 12.2.1 Structure of the processor mode register 1
12–12
b1 b0
Processor mode register 1 (Address 5F
0 0
Bit
1, 0
Fix these bits to "0."
Clock source for peripheral
2
devices select bit
CPU running speed select bit
3
Bus cycle select bits
4
5
Fix these bits to "0."
7, 6
Note: Fix this bit to "0" when f(X
: Bits 0 to 2, 6 and 7 are not used to select the bus cycle.
7751 Group User's Manual
)
16
Bit name
0 : divided by 2
(Note)
1 :
0 : High-speed running
1 : Low-speed running
(Note)
In high-speed running
b5 b4
0 0 : 5
0 1 : 4
1 0 : 3
1 1 : Not selected
In low-speed running
b5 b4
0 0 : Not selected
0 1 : 4
1 0 : 3
1 1 : 2
) > 25 MHz.
IN
Functions
access in high-speed running
access in high-speed running
access in high-speed running
access in low-speed running
access in low-speed running
access in low-speed running
RW
At reset
0 RW
RW
0
RW
0
0 RW
0 RW
RW
0