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SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
[When not using interrupts]
Checking completion of reception
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
b7
Checking error
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
b7
Reading of receive data
UART0 receive buffer register (Addresses 37
UART1 receive buffer register (Addresses 3F
b15
0
0
0
0
0
Checking error
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
b7
Processing after reading out receive data
Fig. 7.4.9 Processing after reception's completion
7–48
b0
1
Receive complete flag
0 : Reception not completed
1 : Reception completed
b0
1
Framing error flag
Parity error flag
Error sum flag
0 : No error
1 : Error detected
, 36
)
16
16
, 3E
)
16
16
b8
b7
0
0
b0
1
Overrun error flag
0 : No overrun error
1 : Overrun error detected
7751 Group User's Manual
[When using interrupts]
The UARTi receive interrupt request
occurs when reception is completed.
)
16
)
16
UARTi receive interrupt
)
16
)
16
b0
Read out receive data.
)
16
)
16
Note : This figure shows the bits and registers required
for processing.
Refer to Figure 7.4.11 about the change of flag
state and the occurrence timing of an interrupt
request.
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