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9.2.2 Operation in Stop mode
In Stop mode, Watchdog timer stops operating. Immediately after Stop mode is terminated, Watchdog timer
operates as follows.
(1) When Stop mode is terminated by a hardware reset
Supply of the φ
CPU
performs the "operation after a reset." (Refer to "Chapter 13. RESET.") The watchdog timer frequency
select bit becomes "0," and Watchdog timer starts counting of Wf
(2) When Stop mode is terminated by an interrupt request occurrence
Immediately after Stop mode is terminated, Watchdog timer starts counting of the count source Wf
Wf
from "FFF
64
16
becomes "0." (At this time, the watchdog timer interrupt request does not occur.)
Supply of the φ
CPU
executes the routine of the interrupt which is used to terminate Stop mode. Watchdog timer restarts
counting of the count source (Note) from "FFF
Note: Clock Wf
9.2.3 Operation in Hold state
Watchdog timer stops operating in Hold state. When Hold state is terminated, Watchdog timer restarts
counting in the same state where it stopped operating.
Hold state : Refer to section "12.4 Hold function."
and φ
starts immediately after Stop mode is terminated, and the microcomputer
BIU
." Supply of the φ
CPU
and φ
starts immediately after Stop mode is terminated, and the microcomputer
BIU
/Wf
or Wf
/Wf
32
64
512
1024
7751 Group User's Manual
and φ
starts when the Watchdog timer's most significant bit
BIU
."
16
which was counted just before executing the STP instruction.
WATCHDOG TIMER
9.2 Operation description
from "FFF
1024
16
."
/
32
9–7
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