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M37751
A
–A
8
23
(D
–D
)
0
15
Address
latch circuit
A
–A
0
7
RDY
E
1
AC04
1
1
Circuit condition: f(X
1
1
E
1Q (AC74)
2Q (AC74)
CS
2
RDY
Fig. 17.1.11 Example of using Ready function (at 4 φ access in high–speed running)
Data bus
Address
CS
1
decode
CS
circuit
2
Address bus
1D
1Q
2D
2Q
1T
2T
2
AC74
) ≤ 28 MHz, 4 access in high–speed running
IN
t
d
(E-
)
1
t
su
(RDY-
)
1
Sum of propagation delay time for BC32
and AC04(max. : 30.5 ns)
7751 Group User's Manual
1 to 4
Use the elements of which sum of
propagation delay time is within 30.5 ns.
4
BC32
BC32
3
Ready function is available
only for areas accessed
by CS
.
2
A
B
t
c
t
su
(RDY-
)
1
2 , AC74,
APPLICATIONS
17.1 Memory expansion
Ready request is accepted at the RDY pin input
level judgment timing A .
Ready state release request is accepted at the
RDY pin input level judgment timing B .
≥ 40 ns
The condition satisfying t
su(RDY- 1)
is tc ≥ 35.25 ns.
) ≤ 28 MHz, this
Accordingly, when f(X
IN
circuit example satisfies t
su(RDY- 1)
: E ( "L" level) stop by Ready function.
≥ 40 ns.
17–15
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