Renesas 7700 FAMILY User Manual page 288

CONNECTION WITH EXTERNAL DEVICES
<When inputting "L" level to
completed with continuous 2-bus cycle>
External data bus
Judgment timing of input
level to HOLD pin
Clock
External address bus /
External data bus
External address bus
BHE
HOLD
HLDA
Notes 1: This figure shows the case of 2 access in low-speed running.
2: Clock
Signals timing to be input or output externally is ordained by clock
3: This term indicated by Note 3 becomes 1.5 cycles in 5 access in high-speed
running. It is because the level judgment timing becomes the 1.5 cycles before the
end of the term using bus (See Table 12.4.2.)
Fig. 12.4.4 Timing of acceptance of Hold request and termination of Hold state (3)
HOLD
State when inputting "L" level to
Data length
16
Using
1
ALE
E
R/W
Address A
Data
Not accepted
Term using bus
When accepting a Hold request, not a new address but an
address output just before is output again.
Hold request cannot be accepted before input/output of 16-bit
data is completed.
has the same polarity and the same frequency as
1
7751 Group User's Manual
pin during term using bus; when data access is
pin
HOLD
External data bus width
8
16
(Access from odd address)
Address A+1
Data
1
1
(Note 3)
12.4 Hold function
Floating
Floating
Address B
Floating
1
1
Hold state
Term using bus
.
BIU
as a basis.
1
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