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b7
b6
b5
b4
b3
b2
0
(b15)
b7
Fig. 5.4.1 Structures of timer Ai mode register and timer Ai register in event counter mode
b1
b0
Timer Ai mode register (i = 0 to 4) (Addresses 56
0 1
Bit
Operating mode select bits
0
1
Pulse output function select bit
2
Count polarity select bit
3
Up-down switching factor select
4
bit
Fix this bit to "0" in event counter mode.
5
6
These bits are ignored in event counter mode.
7
: It may be either "0" or "1."
(b8)
b0 b7
7751 Group User's Manual
Bit name
b1 b0
0 1 : Event counter mode
0 : No pulse output (TAi
functions as a programmable I/O
port.)
1 : Pulse output (TAi
as a pulse output pin.)
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0 : Contents of up-down register
1 : Input signal to TAi
Timer A0 register (Addresses 47
b0
Timer A1 register (Addresses 49
Timer A2 register (Addresses 4B
Timer A3 register (Addresses 4D
Timer A4 register (Addresses 4F
Bit
15 to 0
These bits can be set to "0000
Assuming that the set value = n, the counter
divides the count source frequency by n + 1
when down-counting, or by FFFF
when up-counting.
When reading, the register indicates the
counter value.
TIMER A
5.4 Event counter mode
to 5A
)
16
16
Functions
pin
OUT
pin functions
OUT
pin
OUT
, 46
)
16
16
, 48
)
16
16
, 4A
)
16
16
, 4C
)
16
16
, 4E
)
16
16
Functions
" to "FFFF
."
16
16
– n + 1
16
RW
At reset
0
RW
0
RW
0
RW
0
RW
RW
0
RW
0
0
RW
0
RW
At reset
RW
RW
Undefined
5–21
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