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APPLICATIONS
17.1 Memory expansion
M37751
A
–A
1
7
CNV
SS
BYTE
ALE
A
/D
–
8
8
A
/D
15
15
A
/D
–
16
0
A
/D
23
7
E
1
R/W
BHE
A
0
X
X
OUT
IN
40 MHz
1: Use the elements of which propagation delay time is within 45 ns.
2, 3 : Use the elements of which sum of output disable time in 2 and
propagation delay time in 3 is within 15 ns, and the sum of output
enable time in 2 and propagation delay time in 3 is 5 ns or more.
4: Use the elements of which propagation delay time is within 40 ns.
Fig. 17.1.19 Example for using bus buffer (at high-speed running-2 : connecting with memory requiring
long hold time for write)
17–24
AC573
D Q
LE
OE
AC573
D Q
LE
OE
1D1Q
2D
1T
2T
2Q
AC04
AC74
1
1
AC04
4
AC32
7751 Group User's Manual
Address bus
2
F245
A
B
Data bus (odd)
DIR
OC
2
F245
Data bus (even)
A
B
DIR
OC
3
BC32
This circuit ensures that the rising of the
write signal occurs 1.5
extend the write hold time.
RD
WO
WE
3
AC32
Circuit condition : 5 access in high-speed running
clock earlier to
1
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