Spi Modes With Clock Polarity And Clock Phase - Renesas ForgeFPGA User Manual

ForgeFPGA Configuration Guide
3. MISO: Master-In Slave-Out (data output from slave). MISO is a data pin. This pin is used to transmit data
from the slave to the master. Whenever the slave sends data, that data will be collected over the MISO pin by
the master.
4. SS: Slave-Select (often active low, the output from master). Depending on the SPI and slave select setting,
the SS pin used to select an individual slave device for communication. When there is one master and one slave
device, then the SS pin is not required. This slave select pin will make sense only when the master is
communicating with the different slaves. So, the master can select the slave to which the master wants to
convey. For choosing the slave, the SS pin dedicated.
4.1

SPI Modes with Clock Polarity and Clock Phase

In SPI, the master can select the Clock Polarity (CPOL) and Clock Phase (CPHA). The CPOL bit sets the
polarity of the clock signal during the idle state. The idle state is defined as the period when SS is transitioning.
The CPHA bit selects the clock phase. Depending on the CPHA bit, the rising or falling clock edge is used to
sample and/or shift the data. Depending on the CPOL and CPHA bit selection, four SPI modes are available.
(See Table 2)
Table 2: SPI Modes
SPI
CPOL CPHA
Modes
0 0 0
1 0 1
2 1 1
3 1 0
Figure 3 shows the data on the MOSI and MISO line. The green dotted lines show, the end and the beginning of
the transmission. Also, the data sampling is shown with orange line which corresponds to the rising or falling
edge depending on SPI Mode. The shifting edge of the data is depicted using the blue doted lines.
Rev.1.0
May 31, 2022
Figure 2: SPI Interface
Clock
Polarity in Clock Phase Used to Sample and/or Shift the Data
Idle State
Logic Low Data sampled on rising edge and shifted out on the falling edge
Data sampled on the falling edge and shifted out on the rising
Logic Low
Data sampled on the falling edge and shifted out on the rising
Logic High
Data sampled on the rising edge and shifted out on the falling
Logic High
edge
edge
edge
Figure 3
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