NEC Univerge sv8500 Manual page 2853

The TSW (PH-SW10-A) circuit card includes Phase Lock Oscillator (PLO) functionality. The PLO input leads
appear on the connector shown below, on PIR 0 backplane.
PIR 0
• PLO connector Pin assignment
When the clock is distributed from a digital interface, use one pair of the "DIUxxx" leads among a maximum
of four inputs. The DIU leads have the following precedence: DIU0xx(High)-> DIU3xx(Low). When the
clock is received from an external high-stability oscillator, use the "DCSxx" leads.
for PLO
equipped
with TSW #0
for PLO
equipped
with TSW #1
PLO Pin Assignments for Receiving or Distributing Clock
Phase Lock Oscillator (PLO)
LT 11 / PL 0
LT 10
LT 9
LT 8
for receiving clock from
a High-Stability Oscillator
PIN LEAD PIN LEAD
No. NAME No. NAME
26 DCSB0 1 DCSA0
27 DIU0B0 2 DIU0A0
28 DIU1B0 3 DIU1A0
29 DIU2B0 4 DIU2A0
30 DIU3B0 5 DIU3A0
31 SYN0B0 6 SYN0A0
32 SYN1B0 7 SYN1A0
33 8
40 15
41 16
DCSB1
42 17 DCSA1
DIU0B1
43 18 DIU0A1
DIU1B1
44 19 DIU1A1
DIU2B1
45 20 DIU2A1
DIU3B1
46 21 DIU3A1
SYN0B1
47 22 SYN0A1
SYN1B1
48 23 SYN1A1
49 24
50 25
CHAPTER 3
LT 7
LT 6
LT 5
LBUS 1
LT 4
LBUS 0
for distributing clock from
a digital interface
PIN LEAD
No. NAME
26 DCSB0
for PLO
27 DIU0B0
equipped
28 DIU1B0
with TSW #0
29 DIU2B0
30 DIU3B0
31 SYN0B0
32 SYN1B0
PLO Connector
33
40
41
DCSB1
42
DIU0B1
43
for PLO
DIU1B1
44
equipped
DIU2B1
45
with TSW #1
DIU3B1
46
SYN0B1
47
SYN1B1
48
49
50
VOL.3-366
NETWORK INTERFACE
LT 3
LT 2
LT 1
LT 0
PIN LEAD
No. NAME
1 DCSA0
2 DIU0A0
3 DIU1A0
4 DIU2A0
5 DIU3A0
6 SYN0A0
7 SYN1A0
PLO Connector
8
15
16
17 DCSA1
18 DIU0A1
19 DIU1A1
20 DIU2A1
21 DIU3A1
22 SYN0A1
23 SYN1A1
24
25