Table of Contents
Advertisement
Appendix E: Low Latency Design
Table E-1: GTP Transmitter Latency
Notes:
1. 1 cycle = 1 clock cycle at the TXUSRCLK rate.
GTP Receiver Latency
Figure E-2
Receiver (RX),"
receiver blocks.
1
3
Rx
EQ
Rx
SIPO
CDR
Rx
OOB
2
4
Shared
PMA
PLL
Divider
From Shared PMA PLL
RX-PMA
Table E-2
of the receiver section of the GTP transceiver. The values in the Block Number column
correspond to the circled numbers in
310
Block
Block Name
Number
1
Fabric Interface
2
8B/10B Encoder
3
TX FIFO
4+6+7+8+9
PMA + Interface
Total Latency
shows a detailed block diagram of the GTP receiver. Refer to
and
Figure 7-1, page 123
5
Over-
RX
sampling
Polarity
PRBS
Check
7
RX-PCS
Figure E-2: GTP RX Block Diagram
defines the latency for the specific functional blocks or group of functional blocks
www.xilinx.com
TXDATAWIDTH = 0
1.5 cycles
TXENC8B10BUSE = 0
0 cycles
TX_BUFFER_USE = 0
1 cycle
2 ± 0.5 cycles
Max
10.5 cycles
for more details on this figure and the GTP
6
Comma
Detect
and
10B/8B
Align
8
Decoder
Loss of Sync
9
Figure
E-2.
Virtex-5 RocketIO GTP Transceiver User Guide
Latency
TXDATAWIDTH = 1
2 cycles
TXENC8B10BUSE = 1
1 cycle
TX_BUFFER_USE = 1
1-5 cycles
Min
4 cycles
Chapter 7, "GTP
10
11
Elastic
Buffer
Rx Status Control
12
13
UG196_c7_01_041907
UG196 (v1.3) May 25, 2007
R
14
FPGA
RX
Interface
Advertisement
Table of Contents
