Fpga Rx Interface; Overview; Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 7: GTP Receiver (RX)

FPGA RX Interface

Overview

The FPGA receives RX data from the GTP receiver through the FPGA RX interface. Data is
read from the RXDATA port on the positive edge of RXUSRCLK2.
The width of RXDATA can be configured to be one or two bytes wide. The actual width of
the port depends on the internal data width of the GTP_DUAL, and whether or not the
8B/10B decoder is enabled. Ports widths of 8 bits, 10 bits, 16 bits, and 20 bits are possible.
The rate of the parallel clock (RXUSRCLK2) at the interface is determined by the RX line
rate, the width of the RXDATA port, and whether or not 8B/10B decoding is enabled.
RXUSRCLK must be provided for the internal PCS logic in the receiver. This section shows
how to drive the parallel clocks and explains the constraints on those clocks for correct
operation.

Ports and Attributes

Table 7-34
Table 7-34: FPGA RX Interface Ports
Port Dir
INTDATAWIDTH In
REFCLKOUT Out
RXDATA0
Out
RXDATA1
RXDATAWIDTH0
In
RXDATAWIDTH1
RXRECCLK0
Out
RXRECCLK1
RXRESET In
182
defines the FPGA RX interface ports.
Clock Domain
S
pecifies the bit width for the TX and RX paths. The bit width of TX and RX
must be identical for both channels.
Async
0: 8-bit width
1: 10-bit width
The REFCLKOUT port from each GTP_DUAL tile provides access to the
N/A reference clock provided to the shared PLL (CLKIN). It can be routed for
use in the FPGA logic.
Receive data bus of the receive interface to the FPGA. The width of
RXUSRCLK2
RXDATA(0/1) depends on the setting of RXDATAWIDTH(0/1).
Selects the width of the RXDATA(0/1) receive data connection to the
FPGA.
0: One-byte interface => RXDATA(0/1)[7:0]
RXUSRCLK2
1: Two-byte interface => RXDATA(0/1)[15:0]
The clock domain depends on the selected clock (RXRECCLK(0/1),
RXUSRCLK(0/1), RXUSRCLK2(0/1)) for this interface.
Recovered clock from the CDR. Clocks the RX logic between the PMA
and the RX elastic buffer. Can be used to drive RXUSRCLK
synchronously with incoming data.
N/A
When RXPOWERDOWN[1:0] is set to 11, which is P2 the lowest power
state, then RXRECCLK of this transceiver is indeterminate. RXRECCLK
of this GTP transceiver is either a static 1 or a static 0.
PCS RX system reset. Resets receiver elastic buffer, 8B/10B decoder,
Async comma detect, and other receiver registers. This is a per channel subset
of GTPRESET.
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Description
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Virtex-5 RocketIO GTP Transceiver User Guide
R
UG196 (v1.3) May 25, 2007