Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 6: GTP Transmitter (TX)

Ports and Attributes

Table 6-7
Table 6-7: TX Buffering and Phase-Alignment Ports
Port
PLLLKDET
REFCLKOUT
TXBUFSTATUS0[1:0]
TXBUFSTATUS1[1:0]
TXENPMAPHASEALIGN
TXOUTCLK0
TXOUTCLK1
TXPMASETPHASE
TXUSRCLK0
TXUSRCLK1
104
defines the signals comprising the TX buffering and phase-alignment ports.
Dir Clock Domain
This port indicates that the VCO rate is within acceptable
Out Async tolerances of the desired rate when High. Neither GTP transceiver
in the tile operates reliably until this condition is met.
The REFCLKOUT port from each GTP_DUAL provides direct
Out N/A access to the reference clock provided to the shared PLL (CLKIN).
It can be routed for use in the FPGA logic.
TX buffer status.
TXBUFSTATUS[1]: TX buffer overflow or underflow
1: FIFO has overflowed or underflowed
0: No overflow/underflow error
Out TXUSRCLK2
TXBUFSTATUS[0]:
1: FIFO is at least half full
0: FIFO is less than half full
If TXBUFSTATUS[1] becomes set, it remains set until TXRESET is
asserted.
When activated, both GTP transmitters in a GTP_DUAL tile can
align their XCLKs with their TXUSRCLKs, allowing their TX
In Async
buffers to be bypassed. This also allows the XCLKs in multiple GTP
transmitters to be synchronized to reduce TX skew between them.
This port provides a parallel clock generated by the GTP
transceiver. This clock can be used to drive TXUSRCLK for one or
more GTP transceivers. The rate of the clock depends on
INTDATAWIDTH:
• INTDATAWIDTH = 0:
FTXOUTCLK = Line Rate/8
Out N/A
• INTDATAWIDTH = 1:
FTXOUTCLK = Line Rate/10
Note:
50/50. TXOUTCLK cannot drive TXUSRCLK when the TX phase-
alignment circuit is used.
When activated, TXPMASETPHASE aligns XCLK with
In Async
TXUSRCLK for both GTP transmitters in the GTP_DUAL tile.
Use this port to provide a clock for the internal TX PCS datapath.
This clock must always be provided. Its rate depends on
INTDATAWIDTH:
• INTDATAWIDTH = 0:
In N/A
FTXUSRCLK = Line Rate/8
• INTDATAWIDTH = 1:
FTXUSRCLK = Line Rate/10
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Description
TX buffer fullness
When INTDATAWIDTH = 1, the duty cycle is 60/40 instead of
Virtex-5 RocketIO GTP Transceiver User Guide
R
UG196 (v1.3) May 25, 2007