Example Of A Ucf For Gtp_Dual Placement - Xilinx Virtex-5 RocketIO GTP User Manual

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Example of a UCF for GTP_DUAL Placement

This section shows key elements of a UCF that instantiates seven GTP_DUAL tiles. The file
implements the example configuration shown in
package combination chosen in this example is an XC5VLX110T-FF1136.
The instantiation of the GTP_DUAL tiles and the IBUFDS primitive is typically done in
HDL code within the design hierarchy. That code also connects the output of the IBUFDS
primitive to the CLKIN inputs of the GTP_DUAL tiles, as illustrated by the following
Verilog code fragment:
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
;
; Instantiate the GTP_DUAL tiles in locations X0Y7 to X0Y1
;
INST design_root/gtp_dual[1]/gtp_dual
INST design_root/gtp_dual[2]/gtp_dual
INST design_root/gtp_dual[3]/gtp_dual
INST design_root/gtp_dual[4]/gtp_dual
INST design_root/gtp_dual[5]/gtp_dual
INST design_root/gtp_dual[6]/gtp_dual
INST design_root/gtp_dual[7]/gtp_dual
;
; Connect the REFCLK_PAD_(N/P) differential pair to the middle
; GTP_DUAL tile (GTP_DUAL_X0Y4)
;
NET refclk_pad_n LOC=P4;
NET refclk_pad_p LOC=P3;
//
// Instantiate the GTP_DUAL tiles
//
genvar tile_num;
generate for (tile_num = 1; tile_num <= 7; ++tile_num)
begin: gtp_dual
GTP_DUAL gtp_dual
(
.CLKIN(refclk),
... The remaining GTP_DUAL ports are not shown
)
end
endgenerate
//
// Instantiate the IBUFDS for the reference clock
//
IBUFDS ref_clk_buffer
(
.IN(refclk_pad_n),
.IP(refclk_pad_p),
.O(refclk)
)
www.xilinx.com
Example of a UCF for GTP_DUAL Placement
Figure 5-5, page 71. The device and
LOC=GTP_DUAL_X0Y1;
LOC=GTP_DUAL_X0Y2;
LOC=GTP_DUAL_X0Y3;
LOC=GTP_DUAL_X0Y4;
LOC=GTP_DUAL_X0Y5;
LOC=GTP_DUAL_X0Y6;
LOC=GTP_DUAL_X0Y7;
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