Overview; Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

R
Implementation

Overview

This chapter provides the information needed to map GTP_DUAL tiles instantiated in a
design to device resources, including:
•
•
•
It is a common practice to define the location of GTP transceivers early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis
during board design. The implementation flow facilitates this practice through the use of
location constraints in the UCF.
While this chapter describes how to instantiate GTP_DUAL clocking components, the
details of the different GTP_DUAL tile clocking options are discussed in
68.

Ports and Attributes

Table 4-1
Table 4-1: GTP_DUAL Tile External Ports
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
The location of the GTP_DUAL tiles on the available device and package
combinations.
The pad numbers of external signals associated with each GTP_DUAL tile.
How GTP_DUAL tiles and clocking resources instantiated in a design are mapped to
available locations with a user constraints file (UCF).
shows the external ports associated with each GTP_DUAL tile.
Port
MGTTXP0
MGTTXN0
MGTTXP1
MGTTXN1
MGTRXP0
MGTRXN0
MGTRXP1
MGTRXN1
MGTREFCLKP
MGTREFCLKN
(2)
MGTAVCCPLL
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Dir Domain
Embedded Differential transmit data pairs for
Out
TX Clock GTP transceivers 0 and 1
Embedded Differential receive data pairs for GTP
In
RX Clock transceivers 0 and 1
In N/A Differential reference clock input pair
Analog Analog Pad for 1.2V supply for PLL
Chapter 4
"Clocking," page
Description
49