Xilinx Virtex-5 RocketIO GTP User Manual page 217

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The absolute worst-case scenario would be to supply GTP transceiver analog supplies
from the bottom of the board and have all adjacent SelectIO outputs running at high drive
and high speed and routed to lower routing layers. For more information, refer to
Escape Example," page 252
transceiver analog supply pins.
The SelectIO signals that have the largest impact on GTP transceiver performance are those
whose solder balls are adjacent to GTP transceiver analog supply solder balls (BGA
adjacency).
specific guidance recommendations to optimize GTP transceiver performance in the
presence of SelectIO switching. Specifically, the tables identify those pins which are either
1.0 mm or 1.4 mm away from an GTP transceiver analog supply pin and REFCLK pins. If
a pin is both 1.0 mm and 1.4 mm away from two different GTP transceiver analog supply
pins, then it is only listed in the 1.0 mm column.
Additionally, it is important to properly shield the traces or planes connecting the analog
supply vias to the supply filter network of the analog supplies from SelectIO escaping from
the BGA field. This is best done by placing GND planes above and below the layer
containing the analog traces or planes.
Table 10-6: SelectIO Adjacent to Analog Supplies for (FF665 Packages)
Table 10-7: SelectIO Adjacent to MGTCLK (FF665 Packages)
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
If these SelectIO pins must be used for higher drive/higher speed applications, apply
power to the GTP transceiver analog supplies with a plane or wide buses a few layers
below the top of the board. Using a blind via to the GTP transceiver analog supplies is
better than using a through via. Shield these supply planes or buses with ground
planes above and below.
If a through via to supply the GTP transceiver analog supply pins must be used, use a
layer closes to the FPGA for routing signals to these vias. Route SelectIO nets in the
uppermost layer available after GTP transceiver high-speed signal and GTP
transceiver analog supply routing is implemented.
If supplying GTP transceiver power from the bottom of the board, route these
SelectIO nets in the highest available routing layer.
Table 10-6 through
GTP_DUAL
MGT116
MGT112
MGT114
MGT118
GTP_DUAL
116_REFCLK
112_REFCLK
114_REFCLK
118_REFCLK
www.xilinx.com
SelectIO-to-GTP Crosstalk Guidelines
for information on escaping of SelectIO adjacent to GTP
Table 10-10 provide the GTP transceiver user with pin-
1 mm
E5
L5
U5
AD4
1 mm
D5
K5
T5
AB5
"BGA
1.4 mm
D5, F5, G4
K5
T5, W4
AB5, AD5
1.4 mm
E5
J5, L5
R5, U5
AA5
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