Xilinx Virtex-5 RocketIO GTP User Manual page 166

Chapter 7: GTP Receiver (RX)
data is received because the CDR is not locked, or the CDR is locked and the phase
alignment has not yet been attempted.
To work around this problem, RX phase alignment must be attempted several times and
the output data evaluated after each attempt. Good data is received if the phase is aligned
while the RX CDR is locked.
The flow diagram in
alignment. Any number of clock cycles can be used for the CDR lock time, but using a
larger number decreases the number of cycles through the states.
166
Figure 7-23 shows the series of steps required for successful RX phase
Wait for CDR to Lock
Figure 7-23: Steps Required for Successful RX Phase Alignment
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RESET
Wait for PLL Lock
and DCM/PLL Lock.
RXN/RXP Should Be
Driven
Assert
RXPMASETPHASE
32 RXUSRCLK2
Cycles to
Phase Align
Evaluate CDR Lock by
Fail
Checking Data or Using
LOS State Machine
Pass
Final
RXPMASETPHASE
Assertion for Phase
Alignment with Known
CDR Lock (32 Cycles)
Phase Alignment
Done
UG196_c7_34_102306
Virtex-5 RocketIO GTP Transceiver User Guide
R
UG196 (v1.3) May 25, 2007