Description - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 5: Tile Features

Description

The first step to using the GTP_DUAL tile is to set the output of the shared PLL (PLL clock)
to a rate that can be used by each GTP transceiver to generate an appropriate serial line rate
and corresponding parallel clock rate. Both GTP TX and RX blocks are equipped with an
independent divider that can divide the PLL clock by a factor of 1, 2, or 4. This divider
allows the TX and RX blocks of each GTP transceiver to run at different rates, related by an
integer multiple.
The PLL clock rate must be set to one-half the required line rate before the independent
dividers. For example, if an RX line rate of 2.5 Gb/s is desired in GTP0, and the
independent divider in the GTP RX block is set to 1, the PLL clock should be set to
1.25 GHz.
The shared PMA PLL has a nominal operation range. The Virtex-5 Data Sheet specifies the
operating range of the shared PLL including the marginal conditions. Set the PLL clock
must be within this operating range.
CLKIN (the reference clock), PLL_DIVSEL_FB, PLL_DIVSEL_REF, and INTDATAWIDTH.
PLL_DIVSEL_FB and PLL_DIVSEL_REF control dividers inside the PLL.
INTDATAWIDTH controls the internal parallel data width of the entire GTP_DUAL tile.
Equation 5-1
The following conditions apply to
•
•
•
•
•
The programmable dividers allow support for various standards.
Figure 5-2
generated.
62
shows how to set the rate of the PLL clock.
f f
=
PLL Clock CLKIN
PLL_DIVSEL_REF = [1, 2]
PLL_DIVSEL_FB = [1, 2, 3, 4, 5]; where 3 and 5 cannot be used when
INTDATAWIDTH = 0.
When PLL_DIVSEL_FB = 1, set PCS_COM_CFG to 28'h1680A07, otherwise set to
28 ' h1680A0E (default)
If INTDATAWIDTH = 1, DIV = 5, otherwise DIV = 4
The PLL clock frequency range is as specified in the Virtex-5 Data Sheet
The smallest possible divider values must be selected
shows a conceptual view of the shared PLL from which the PLL clock is
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Equation 5-1 shows how to set the PLL clock based on
×
PLL_DIVSEL_FB DIV
×
--------------------------------------------------------------- -
PLL_DIVSEL_REF
Equation 5-1:
Virtex-5 RocketIO GTP Transceiver User Guide
R
Equation 5-1
UG196 (v1.3) May 25, 2007