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Table 7-34: FPGA RX Interface Ports (Continued)
Port
Dir
RXUSRCLK0
In
RXUSRCLK1
RXUSRCLK20
In
RXUSRCLK21
Notes:
1. 10-bit internal data width is necessary when the RX buffer is bypassed.
There are no attributes in this section.
Description
The FPGA RX interface allows parallel received data to be read from the GTP transceiver.
For this interface to be used, the following must be done:
•
•
Configuring the Width of the Interface
Table 7-35
discussed in more detail in
Table 7-35: RX Datapath Width Configuration
INTDATAWIDTH
Notes:
1. 10-bit internal data width is necessary when the RX buffer is bypassed.
2. The internal datapath is 8 bits when INTDATAWIDTH = 0 and 10 bits when INTDATAWIDTH = 1.
3. The RXDATA interface is one byte wide when RXDATAWIDTH = 0 and two bytes wide when
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Clock Domain
Input clock used for internal RX logic after the RX FIFO. Generally,
N/A
RXUSRCLK0/1 runs at either 1/8 or 1/10 the RX baud rate, which for
some standards is identical to TXUSRCLK0/1.
Input clock used for the interface between the FPGA and the GTP
transceiver. For a one-byte interface, RXUSRCLK20/1 is equal to
N/A
RXUSRCLK0/1. For a two-byte interface, RXUSRCLK20/1 runs at one-
half RXUSRCLK0/1. For some standards, TXUSRCLK20/1 is identical to
TXUSRCLK20/1.
The width of the RXDATA port must be configured
RXUSRCLK2 and RXUSRCLK must be connected to clocks running at the correct rate.
shows how to select the interface width for the RX datapath. 8B/10B decoding is
"Configurable 8B/10B Decoder," page
(1,2)
RXDATAWIDTH
0
0
1
1
1
1
RXDATAWIDTH = 1.
www.xilinx.com
Description
(3)
RXDEC8B10BUSE
N/A
0
N/A
1
0
0
0
1
1
0
1
1
FPGA RX Interface
157.
FPGA RX Interface Width
8 bits
16 bits
10 bits
8 bits
20 bits
16 bits
183
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