Xilinx Virtex-5 RocketIO GTP User Manual page 171

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Table 7-31: Clock Correction Attributes (Continued)
Attribute
CLK_COR_DET_LEN_0
CLK_COR_DET_LEN_1
CLK_COR_INSERT_IDLE_FLAG_0
CLK_COR_INSERT_IDLE_FLAG_1
CLK_COR_KEEP_IDLE_0
CLK_COR_KEEP_IDLE_1
CLK_COR_MAX_LAT_0
CLK_COR_MAX_LAT_1
CLK_COR_MIN_LAT_0
CLK_COR_MIN_LAT_1
CLK_COR_PRECEDENCE_0
CLK_COR_PRECEDENCE_1
CLK_COR_REPEAT_WAIT_0
CLK_COR_REPEAT_WAIT_1
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
This attribute defines the length of the sequence that the transceiver matches to
detect opportunities for clock correction. Valid lengths are from one to four bytes.
Controls whether RXRUNDISP input status indicates running disparity or
inserted-idle (clock correction sequence) flag.
FALSE: RXRUNDISP indicates running disparity when RXDATA is decoded
data.
TRUE: RXRUNDISP is raised for the first byte of each inserted (repeated)
clock correction ("Idle") sequence (when RXDATA is decoded data).
Controls whether the elastic buffer must retain at least one clock correction
sequence in the byte stream.
FALSE: Transceiver can remove all clock correction sequences to further re-
center the elastic buffer during clock correction.
TRUE: In the final RXDATA stream, the transceiver must leave at least one
clock correction sequence per continuous stream of clock correction
sequences.
Specifies the maximum elastic buffer latency. If the elastic buffer exceeds
the clock correction circuit removes incoming clock
CLK_COR_MAX_LAT,
correction sequences to prevent overflow. Valid values for this attribute range
from 3 to 48.
Specifies the minimum elastic buffer latency. If the elastic buffer drops below
the clock correction circuit replicates incoming clock
CLK_COR_MIN_LAT,
correction sequences to prevent underflow
When the elastic buffer is reset, its pointers are set so there are
CLK_COR_MIN_LAT unread (and uninitialized) data bytes in the buffer.
Valid values for this attribute range from 3 to 48.
Determines whether clock correction or channel bonding takes precedence when
both operations are triggered at the same time.
TRUE: Clock correction takes precedence over channel bonding if there is
opportunity for both
FALSE: Channel bonding takes precedence over clock correction if there is
opportunity for both
This attribute specifies the minimum number of RXUSRCLK cycles without
clock correction that must occur between successive clock corrections. If this
attribute is zero, no limit is placed on how frequently clock correction can occur.
Valid values for this attribute range from 0 to 31.
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Configurable Clock Correction
Description
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