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Chapter 6: GTP Transmitter (TX)
Table 6-21
Table 6-21: TX OOB/Beacon Signaling Attributes
Description
The GTP_DUAL tile supports two OOB/beacon signaling modes: one for SATA and one
for PCI Express. The use of these two mechanisms is mutually exclusive.
PCI Express Beacon Signaling
Beacon signaling for PCI Express is performed when the GTP_DUAL tile is in the P2
power state. Transmission of a beacon is initiated by the deassertion of TXELECIDLE, as
shown in
TXELECIDLE.
TXPOWERDOWN[1:0]
SATA OOB Signaling
OOB signaling for SATA is initiated though the use of the TXCOMSTART and
TXCOMTYPE ports. Assertion of TXCOMSTART for one TXUSRCLK2 cycle initiates the
transmission of a COM sequence. The type of COM sequence generated is controlled by
the TXCOMTYPE port as shown in
The number of bursts in the COM sequence is controlled by the COM_BURST_VAL
attribute. The timing of the COM sequences transmitted is correct as long as the PLL clock
120
defines the OOB/beacon signaling attributes.
Attribute
COM_BURST_VAL_0
COM_BURST_VAL_1
PLL_SATA_0
PLL_SATA_1
PLL_TXDIVSEL_COMM_OUT
PLL_TXDIVSEL_OUT_0
PLL_TXDIVSEL_OUT_1
Figure
6-18. FPGA control logic controls beacon timing by the sequencing of
TXELECIDLE
TXN/TXP
Figure 6-18: PCI Express Beacon Generation
www.xilinx.com
Number of bursts in a COM sequence
Tie to FALSE. When FALSE, PLL_SATA allows TX SATA
operations to work at the SATA1 or SATA2 rate.
Sets the common divider for the TX line rate. If either
PLL_TXDIVSEL_OUT is not equal to 1,
PLL_TXDIVSEL_COMM_OUT must be set to 1. Can be set
to 1, 2, or 4.
Sets the divider for the TX line rate for the individual GTP
transceiver. If PLL_TXDIVSEL_COMM_OUT is not equal
to 1, PLL_TXDIVSEL_OUT must be set to 1. Can be set to
1, 2, or 4.
'11'
Valid Beacon Signaling
Table
6-20.
Virtex-5 RocketIO GTP Transceiver User Guide
Description
UG196_c6_18_102306
UG196 (v1.3) May 25, 2007
R
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