Xilinx Virtex-5 RocketIO GTP User Manual page 208

Chapter 10: GTP-to-Board Interface
Figure 10-8
Figure 10-9
reference clock input pair MGTREFCLKP/MGTREFCLKN is internally terminated with
100Ω differential impedance. The common mode voltage of this differential reference clock
input pair is 2/3 of MGTAVCCPLL.
If the common mode voltage of the driving clock source is different from the common
mode voltage of the differential reference clock input pair, then AC coupling capacitors are
mandatory to prevent device degradation and/or other damage.
208
shows the rise and fall time convention of the reference clock.
80%
20%
T
FCLK
Figure 10-8: Rise and Fall Time
illustrates the internal details of the IBUFDS. The dedicated differential
MGTREFCLKP
MGTREFCLKN
Notes:
1. Nominal values. Refer to the Virtex-5 Data Sheet for exact specifications.
Figure 10-9: IBUFDS Details
www.xilinx.com
T
RCLK
50Ω (1)
2
MGTAVCCPLL
3
50Ω (1)
Virtex-5 RocketIO GTP Transceiver User Guide
UG196_c10_08_100506
to GTP
Dedicated
Clock
REFCLK
Routing
UG196_c10_09_042807
UG196 (v1.3) May 25, 2007
R