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R
Table 1-3: GTP_DUAL Port Summary (Continued)
Port
INTDATAWIDTH
LOOPBACK0[2:0]
LOOPBACK1[2:0]
PHYSTATUS0
PHYSTATUS1
PLLLKDET
PLLLKDETEN
PLLPOWERDOWN
PRBSCNTRESET0
PRBSCNTRESET1
REFCLKOUT
REFCLKPWRDNB
RESETDONE0
RESETDONE1
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Dir
Domain
Sets the internal datapath width for the
GTP_DUAL tile.
In
Async
0: 8-bit internal datapath width
1: 10-bit internal datapath width
In
Async
Sets the loopback mode.
Indicates completion of several PHY
functions, including power
Out
Async
management state transitions and
receiver detection.
Indicates that the VCO rate is within
Out
Async
acceptable tolerances of the desired
rate.
In
Async
Enables the PLL lock detector.
In
Async
Powers down the shared PMA PLL.
In
RXUSRCLK2
Resets the PRBS error counter.
Provides access to the reference clock
Out
N/A
provided to the shared PLL (CLKIN).
Powers down the GTP reference clock
In
Async
circuit (active Low).
Indicates when the GTP transceiver has
Out
Async
finished reset and is ready for use.
www.xilinx.com
Description
Ports and Attributes
Section (Page)
Shared PMA PLL
(page 61),
FPGA TX
Interface
(page 90),
Parallel In to Serial Out
(PISO)
(page 110),
Configurable RX Elastic
Buffer and Phase
Alignment
(page 162),
Configurable Clock
Correction
(page 169),
Configurable Channel
Bonding (Lane Deskew)
(page 176),
FPGA RX
Interface
(page 182)
Loopback
(page 196)
PCI Express Receive
Detect Support
(page 116)
Shared PMA PLL
(page 61)
Shared PMA PLL
(page 61)
Power Control
(page 81)
PRBS Detection
(page 147)
Shared PMA PLL
(page 61),
Clocking
(page 70),
FPGA TX
Interface
(page 90),
TX
Buffering, Phase
Alignment, and Buffer
Bypass
(page 104),
FPGA RX Interface
(page 182)
Power Control
(page 81)
Reset
(page 73),
RX
Clock Data Recovery
(CDR)
(page 136)
25
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