Xilinx Virtex-5 RocketIO GTP User Manual page 31

R
Table 1-3: GTP_DUAL Port Summary (Continued)
Port
TXPOWERDOWN0[1:0]
TXPOWERDOWN1[1:0]
TXPREEMPHASIS0[2:0]
TXPREEMPHASIS1[2:0]
TXRESET0
TXRESET1
TXRUNDISP0[1:0]
TXRUNDISP1[1:0]
TXUSRCLK0
TXUSRCLK1
TXUSRCLK20
TXUSRCLK21
Table 1-4
descriptions.
Table 1-4: GTP_DUAL Attribute Summary
Attribute
AC_CAP_DIS_0
AC_CAP_DIS_1
ALIGN_COMMA_WORD_0
ALIGN_COMMA_WORD_1
CHAN_BOND_1_MAX_SKEW_0
CHAN_BOND_1_MAX_SKEW_1
CHAN_BOND_2_MAX_SKEW_0
CHAN_BOND_2_MAX_SKEW_1
CHAN_BOND_LEVEL_0
CHAN_BOND_LEVEL_1
CHAN_BOND_MODE_0
CHAN_BOND_MODE_1
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Dir Domain
In Async Powers down TX lanes.
Controls the relative strength of the
In Async
main drive and the pre-emphasis.
Resets the PCS of the GTP transmitter,
including the phase adjust FIFO, the
In Async
8B/10B encoder, and the FPGA TX
interface.
Indicates the current running disparity
Out TXUSRCLK2
of the 8B/10B encoder.
Provides a clock for the internal TX PCS
In N/A
datapath.
Synchronizes the FPGA logic with the
In N/A
TX interface.
summarizes the GTP_DUAL tile attributes and provides links to their detailed
Description
Disables built-in AC coupling capacitors on
receiver inputs when set to TRUE.
Controls alignment of detected commas
within a multi-byte datapath.
Sets the maximum amount of lane skew
allowed when using channel bonding. Must
be set less than 1/2 the minimum distance
between channel bonding sequences.
Indicates the amount of internal pipelining
used for the elastic buffer control signals.
Defines the channel bonding mode of
operation for the transceiver.
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Description
RX Termination and
Equalization
Configurable Comma
Alignment and Detection
(page 151)
Configurable Channel Bonding
(Lane Deskew)
Configurable Channel Bonding
(Lane Deskew)
Configurable Channel Bonding
(Lane Deskew)
Ports and Attributes
Section (Page)
Power Control
(page 81), PCI Express
Receive Detect Support
(page 117), TX
OOB/Beacon Signaling
(page 119)
Configurable TX Driver
(page 113)
Reset (page 73), FPGA
TX Interface (page 91)
Configurable 8B/10B
Encoder (page 100)
FPGA TX Interface
(page 91), TX Buffering,
Phase Alignment, and
Buffer Bypass (page 104)
FPGA TX Interface
(page 91)
Section (Page)
(page 126)
(page 176)
(page 177)
(page 177)
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