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Chapter 7: GTP Receiver (RX)
Figure 7-34
bits (INTDATAWIDTH = 0) and 8B/10B decoding is disabled.
Received
Last
RXDATA
15
14
13
12
Figure 7-34: RX Interface with 8B/10B Bypassed (8-Bit Internal Datapath)
Figure 7-35
(INTDATAWIDTH = 1) and 8B/10B decoding is disabled. When RXDATA is 10 bits or 20
bits wide, the RXDISPERR and RXCHARISK ports are taken from the 8B/10B decoder
interface and are used to present the extra bits.
Received
Last
RXDATA
15 14 13 12 11 10 9
RXDATAWIDTH = 1
RXCHARISK[1]
RXDISPERR[1]
Figure 7-35: RX Interface with 8B/10B Bypassed (10-Bit Internal Datapath)
When 8B/10B decoding is used, the data interface is a multiple of 8 bits like in
but the data is decoded before it is presented at the RXDATA port. Refer to
8B/10B Decoder," page 157
decoding.
Connecting RXUSRCLK and RXUSRCLK2
The FPGA RX Interface includes two parallel clocks: RXUSRCLK and RXUSRCLK2.
RXUSRCLK is the internal clock for the PCS logic in the GTP receiver. The required rate for
RXUSRCLK depends on the internal datapath width of the GTP_DUAL tile
(INTDATAWIDTH), and the RX line rate of the GTP receiver (see
(SIPO)," page 141
calculate the required rate for RXUSRCLK.
RXUSRCLK2 is the main synchronization clock for all signals into the RX side of the GTP
transceiver. Most signals into the RX side of the GTP receiver are sampled on the positive
edge of RXUSRCLK2. RXUSRCLK2 is the same rate at RXUSRCLK when RXDATAWIDTH
184
shows how RXDATA is received serially when the internal datapath is eight
INTDATAWIDTH = 0 and RXDEC8B10BUSE = 0
11
10
9
8
7
6
RXDATAWIDTH = 1
shows how RXDATA is received serially when the internal datapath is 10 bits
INTDATAWIDTH = 1 and RXDEC8B10BUSE = 0
8
7
RXCHARISK[0]
RXDISPERR[0]
to see how RX line rate is determined).
RXUSRCLK Rate
www.xilinx.com
Received
First
5
4
3
2
1
0
Received
First
6
5
4
3
2
1
0
for more details about bit ordering when using 8B/10B
Line Rate
=
---------------------------------------------------------------- -
Internal Datapath Width
Virtex-5 RocketIO GTP Transceiver User Guide
Received
Last
7
6
5
4
3
2
RXDATAWIDTH = 0
UG196_c7_31_100506
Received
Last
7
6
5
4
3
RXDATAWIDTH = 0
RXCHARISK[0]
RXDISPERR[0]
UG196_c7_32_100506
Figure
"Configurable
"Serial In to Parallel Out
Equation 7-7
shows how to
Equation 7-7
UG196 (v1.3) May 25, 2007
R
Received
First
1
0
Received
First
2
1
0
7-34,
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