Xilinx Virtex-5 RocketIO GTP User Manual page 228

Chapter 11: Design Constraints Overview
To calculate the blocking capacitor value, several factors must be known:
•
•
•
•
From
The voltage drop can be calculated using
where:
•
•
The slope is defined by
Substituting
To demonstrate the use of
a serial link running at 3.125 Gb/s using 8B/10B line coding. This example uses the
following assumptions:
•
•
•
•
•
228
V1
V2
t : The rise time of the signal
r
T: The bit period
N : The maximum number of consecutive identical digits (CIDs)
CID
PDJ: The amount of pattern dependent jitter that can be tolerated by the system
Figure 11-5 it can be seen that PDJ can be estimated by:
Δ
V
τ is the RC time constant (C is the ac coupling capacitor, R = 2 x R
t is the total discharge time, which is equal to N
Equation
slope
Equation 11-2 and
C
= ------------------------------------------------------------------------- -
×
2
Equation
Bit period (T) = 3.200 x 10
Signal rise time (t )
r
Pattern Dependent Jitter (PDJ) = 3.200 x 10-12 (0.01 UI)
Consecutive Identical Digits (N
Termination Resistance (R
www.xilinx.com
ΔV
80%
20%
PDJ
Figure 11-5: PDJ Detail
Δ
V
PDJ
= ------------ -
slope
Equation 11-2:
t – τ ⁄
( )
= 0.5V 1 e –
PP
CID
11-3:
0.6
×
------ -
= V
PP
t
r
Equation 11-3 into Equation 11-1
×
– T N
CID
⎛ ⎞
1.2PDJ
×
R ln 1 – ------------------
⎝ ⎠
TERM
t
r
11-4, calculate the blocking capacitor value needed for
-10
(3.125 Gb/s)
= 6.400 x 10-11 (0.2 UI)
) = 5 (guaranteed by 8B/10B)
CID
) = 75 Ω
TERM
Virtex-5 RocketIO GTP Transceiver User Guide
t
r
VTH
UG196_c11_05_092006
Equation 11-1
Equation 11-2
).
TERM
T.
Equation 11-3
and solving for C gives:
Equation 11-4
UG196 (v1.3) May 25, 2007
R