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R
The horizontal sample point shift is not supported for PLL_RXDIVSEL_OUT = 2 or
PLL_RXDIVSEL_OUT = 4.
Table 7-12: Settings for PMA_CDR_SCAN based on PLL_RXDIVSEL_OUT
PLL_RXDIVSEL_OUT
1
Notes:
1. 8'h76 = Do not change from the default value set by the RocketIO GTP Transceiver Wizard. When changing the lower bits of
PMA_CDR_SCAN, the upper bits must be masked to prevent an accidental change from the default value.
Serial In to Parallel Out (SIPO)
Overview
The Serial In to Parallel Out (SIPO) block deserializes serial data from the GTP receiver
PMA and presents it as parallel data to the PCS.
Ports and Attributes
Table 7-13
Table 7-13: SIPO Ports
Table 7-14
Table 7-14: SIPO Attributes
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
[26]
[25]
[24]
1
1
0
defines the SIPO ports.
Port
Dir
INTDATAWIDTH
defines the SIPO attributes.
Attribute
OVERSAMPLE_MODE
PLL_RXDIVSEL_OUT_0
PLL_RXDIVSEL_OUT_1
www.xilinx.com
PMA_CDR_SCAN
[23:16]
(1)
8'h76
Clock Domain
In
Async
This shared attribute activates the built-in 5x digital oversampling
circuits in both GTP_DUAL transceivers. Oversampling must be
enabled when running the GTP transceivers at line rates between
100 Mb/s and 500 Mb/s.
TRUE: Built-in 5x digital oversampling enabled for both GTP
transceivers on the tile
FALSE: Digital oversampling disabled
See
"Oversampling," page 143
oversampling.
This divider defines the nominal line rate for the receiver. It can be
set to 1, 2, or 4.
RX Line Rate = PLL Clock * 2/PLL_RXDIVSEL_OUT
Serial In to Parallel Out (SIPO)
[15:8]
(1)
8'h00 - 8'h80
8'h76
Description
Specifies the width of the internal
datapath for the entire GTP_DUAL
tile. This shared port is also described
in
"Shared PMA PLL," page
0: Internal datapath is 8 bits wide
1: Internal datapath is 10 bits wide
Description
for more details about 5x digital
[7:0]
60.
141
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