Figure 2-9: Low-Latency Clocking; Common Mgt Clocking Use Cases - Xilinx Virtex-4 RocketIO User Manual

Chapter 2: Clocking, Timing, and Resets

Common MGT Clocking Use Cases

Figure 2-9
Note:
clocking. A connection of these clocks to BUFG is possible with the use of fabric interconnect.
76
and Figure 2-10
TXOUTCLK1/TXOUTCLK2 / RXRECCLK1/RXRECCLK2 connect to local and regional
Reference Clock
(1)
BUFR
User DATA
User DATA
synchronous to
recovered clock
(1)
BUFR
No latency
requirement to regional
or global clock tree
since phase alignment is handled in MGT.
Notes: 1. BUFG connect is possible with TXOUTCLK1 or RXRECCLK1 with the use of fabric interconnect.
www.xilinx.com
show the common clocking use models that the MGT supports.
The PMA has parallel clock dividers
that can provide TXOUTCLK1 to the
1-byte, 2-byte, or 4-byte USRCLK2
REFCLK
TXOUTCLK1
TXDATA
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
ETC.
TXUSRCLK2
TXUSRCLK
RXUSRCLK2
RXUSRCLK
RXDATA
RXCHARISCOMMA
RXRUNDISP
RXCHARISK
ETC.
RXRECCLK1
GT11

Figure 2-9: Low-Latency Clocking

PCS has internal dividers
to generate the /1, /2, or
/4 USRCLKs.
The PMA has parallel clock
dividers that can provide
RXRECCLK1 to the 1-byte,
2-byte,or 4-byte USRCLK2.
ug076_ch2_10_061507
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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