Xilinx Virtex-5 RocketIO GTP User Manual page 56

Chapter 4: Implementation
XC5VLX110T: Not Available
XC5VLX220T: Not Available
XC5VLX330T: GTP_DUAL_X0Y11
XC5VLX110T: Not Available
XC5VLX220T: Not Available
XC5VLX330T: GTP_DUAL_X0Y10
XC5VLX110T: GTP_DUAL_X0Y7
XC5VLX220T: GTP_DUAL_X0Y7
XC5VLX330T: GTP_DUAL_X0Y9
XC5VLX110T: GTP_DUAL_X0Y6
XC5VLX220T: GTP_DUAL_X0Y6
XC5VLX330T: GTP_DUAL_X0Y8
Figure 4-5: XC5VLX110T-FF1738, XC5VLX220T-FF1738, and XC5VLX330T-FF1738 GTP Placement (1 of 3)
56
Right Edge of the Die
D16
C16
A14
A15
A17
A16
B13
B14
B18
B17
D10
C10
A8
A9
A11
A10
B7
B8
B12
B11
C4
C3
A2
A3
A5
A4
B1
B2
B6
B5
F4
F3
H1
G1
E1
F1
J2
H2
D2
E2
www.xilinx.com
C14
MGTREFCLKP_132
MGTREFCLKN_132
C15 MGTAVCC_132
MGTRXP1_132
D15
MGTRXN1_132
C17
MGTRXP0_132
MGTRXN0_132
C13
MGTTXP1_132
C18 MGTAVTTTX_132
MGTTXN1_132
MGTTXP0_132
MGTTXN0_132
C8
MGTREFCLKP_128
MGTREFCLKN_128
C9
MGTRXP1_128
D9
MGTRXN1_128
C11
MGTRXP0_128
MGTRXN0_128
C12
MGTTXP1_128
C7
MGTTXN1_128
MGTTXP0_128
MGTTXN0_128
MGTREFCLKP_124 C2
MGTREFCLKN_124
MGTRXP1_124 D4
MGTRXN1_124 D5
MGTRXP0_124 C5
MGTRXN0_124
MGTTXP1_124 C1
MGTTXN1_124 C6
MGTTXP0_124
MGTTXN0_124
H3
MGTREFCLKP_120
MGTREFCLKN_120
G3
MGTRXP1_120
G4
MGTRXN1_120
E3
MGTRXP0_120
MGTRXN0_120
D3
MGTTXP1_120
J3
MGTTXN1_120
MGTTXP0_120
MGTTXN0_120
Virtex-5 RocketIO GTP Transceiver User Guide
R
Power Pins
MGTAVCCPLL_132
MGTAVCC_132
MGTAVTTRX_132
MGTAVTTTX_132
MGTAVCCPLL_128
MGTAVCC_128
MGTAVCC_128
MGTAVTTRX_128
MGTAVTTTX_128
MGTAVTTTX_128
MGTAVCCPLL_124
MGTAVCC_124
MGTAVCC_124
MGTAVTTRX_124
MGTAVTTTX_124
MGTAVTTTX_124
MGTAVCCPLL_120
MGTAVCC_120
MGTAVCC_120
MGTAVTTRX_120
MGTAVTTTX_120
MGTAVTTTX_120
UG196_c4_05_110906
UG196 (v1.3) May 25, 2007