Xilinx Virtex-5 RocketIO GTP User Manual page 311

R
Table E-2: GTP Receiver Latency
Block Number Block Name
14 Fabric Interface
10 8B/10B Encoder
11 RX FIFO
8 Comma Alignment
5+6 Oversampling
1+2+3+4 PMA + Interface
Total Latency
Not oversampling
Notes:
1. 1 cycle = 1 clock cycle at the RXUSRCLK rate.
2. When the RX buffer is bypassed, 10-bit internal data width is necessary, therefore, INTDATAWIDTH = 1.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
RXDATAWIDTH = 0
2 cycles
RXDEC8B10BUSE = 0
0 cycles
RX_BUFFER_USE = 0
2 cycles
RXCOMMADETUSE = 0
2 cycles
OVERSAMPLE_MODE = FALSE
1 cycle
1.5 ± 1 cycle
Max
13.5 + CLK_COR_MIN_LAT
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GTP Receiver Latency
Latency
RXDATAWIDTH = 1
3 cycles
(2)
RXDEC8B10BUSE = 1
1 cycle
RX_BUFFER_USE = 1
2 cycles + CLK_COR_MIN_LAT
RXCOMMADETUSE = 1
2-4 cycles
OVERSAMPLE_MODE = TRUE
Min
7.5 cycles
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