Description - Xilinx Virtex-5 RocketIO GTP User Manual

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Table 7-10
Table 7-10: RX CDR Attributes

Description

Before serial data received from the line can be used, the embedded clock in the signal
must be recovered. The CDR circuit in each GTP transceiver is responsible for this
function. It takes a divided, high-speed serial clock from the shared PLL and adjusts its
phase and frequency until its transitions match the incoming data. As shown in
the result is a clock that matches the clock originally used to generate the serial stream.
Because transitions in the incoming data are used to recover the serial clock, long runs
without transitions can introduce error. The RX CDR circuit can tolerate runs longer than
150 bits, but designers should take steps to limit the length of runs without transitions to
150 bits or fewer.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
defines the RX CDR attributes.
Attribute
PMA_CDR_SCAN_0
PMA_CDR_SCAN_1
PMA_RX_CFG_0
PMA_RX_CFG_1
PLL_RXDIVSEL_OUT
Incoming Serial Data
Figure 7-4: Conceptual View of RX CDR Circuit
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RX Clock Data Recovery (CDR)
Description
This 27-bit attribute allows direct control of the CDR
sampling point. In normal operation, this attribute
should be left at the default value set by the RocketIO
GTP Transceiver Wizard.
This 25-bit attribute allows the operation of the CDR to
be adjusted for tests. In normal operation, this attribute
must be left at the default value set by the RocketIO GTP
Transceiver Wizard.
GTP_DUAL
Shared PLL
Divide by
{1, 2, 4}
PLL Clock/PLL_RXDIVSEL_OUT
Serial Data
RX CDR
Circuit
Recovered Serial Clock
Figure 7-4,
UG196_c7_04_012607
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