Receiver Overview - Xilinx Virtex-5 RocketIO GTP User Manual

R
GTP Receiver (RX)
This chapter shows how to configure and use each of the functional blocks inside the GTP
receiver.

Receiver Overview

Each GTP transceiver includes an independent receiver, made up of a PCS and a PMA.
Figure 7-1
traces on the board into the PMA of the receiver, into the PCS, and finally into the FPGA
logic. Refer to
diagram.
1
3
Rx
EQ
Rx
SIPO
CDR
Rx
OOB
2 4
Shared
PMA
PLL
Divider
From Shared PMA PLL
RX-PMA
The key elements within the GTP receiver are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
shows the functional blocks of the receiver. High-speed serial data flows from
Appendix E, "Low Latency Design,"
6
5
Over- RX
sampling Polarity
PRBS
Check
7
RX-PCS
Figure 7-1: GTP RX Block Diagram
"RX Termination and Equalization," page 125
"RX OOB/Beacon Signaling," page 129
"RX Clock Data Recovery (CDR)," page 136
"Serial In to Parallel Out (SIPO)," page 141
"Oversampling," page 143
"RX Polarity Control," page 146
"PRBS Detection," page 147
"Configurable Comma Alignment and Detection," page 148
"Configurable Loss-of-Sync State Machine," page 155
www.xilinx.com
for latency information on this block
Comma
10
Detect
and
10B/8B
Align
Decoder
8
Loss of Sync
9
12
Chapter 7
11
Elastic
Buffer
Interface
Rx Status Control
13
UG196_c7_01_041907
14
FPGA
RX
123