Refclkout Driving Multiple Transceivers With A 2-Byte Interface - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 6: GTP Transmitter (TX)

REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface

Figure 6-8
REFCLKOUT runs continuously, even when the GTP_DUAL tile is reset; however, extra
clocking resources might be needed to generate the correct USRCLK frequency. In
Figure
REFCLKOUT. A DCM can be used instead of the PLL, but the PLL is more convenient
when the REFCLKOUT rate is not an integer multiple of the required TXUSRCLK rates.
96
PLLLKDET
TXOUTCLK
GTP
TXUSRCLK2
Transceiver
TXUSRCLK
TXDATA (16 or 20 bits)
GTP
TXUSRCLK2
Transceiver
TXUSRCLK
TXDATA (16 or 20 bits)
Figure 6-7: TXOUTCLK Drives Multiple GTP Transceivers with a 2-Byte Interface
shows how REFCLKOUT can be used to generate USRCLK signals.
6-8, a PLL is used to generate the TXUSRCLK and TXUSRCLK2 frequencies from
www.xilinx.com
TXUSRCLK
Selected
TXUSRCLK2
Divide-by-2
LOCKED
Solution
Virtex-5 RocketIO GTP Transceiver User Guide
R
Design in
FPGA
UG196_c6_07_040709
UG196 (v1.3) May 25, 2007