Xilinx Virtex-5 RocketIO GTP User Manual page 38

Chapter 1: Introduction to the RocketIO GTP Transceiver
Table 1-4: GTP_DUAL Attribute Summary (Continued)
Attribute
TX_XCLK_SEL_0
TX_XCLK_SEL_1
TXRX_INVERT0
TXRX_INVERT1
38
Description
Selects the clock used to drive the clock
domain in the PCS following the TX buffer.
Set to TXOUT (TXOUTCLK) when using
the TX buffer. Set to TXUSR (TXUSRCLK)
when bypassing the TX buffer.
Controls inverters that optimize the clock
paths within the GTP transceiver. When
bypassing the TX buffer, set to 00100.
Otherwise, set to 00000.
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Section (Page)
TX Buffering, Phase Alignment,
and Buffer Bypass
TX Buffering, Phase Alignment,
and Buffer Bypass
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
R
(page 105)
(page 105)