Table of Contents
Advertisement
Chapter 1: Introduction to the RocketIO GTP Transceiver
Table 1-2: GTP_DUAL Analog Pin Summary (Continued)
Table 1-3
descriptions.
Table 1-3: GTP_DUAL Port Summary
Port
CLKIN
DADDR[6:0]
DCLK
DEN
DI[15:0]
DO[15:0]
DRDY
DWE
GTPRESET
GTPTEST[3:0]
24
Pin
Dir
MGTRXN0
MGTRXP0
In
MGTRXN1
MGTRXP1
MGTTXN0
MGTTXP0
In Pad
MGTTXN1
MGTTXP1
summarizes all GTP_DUAL ports and provides links to their detailed
Dir
Domain
In
Async
In
DCLK
In
N/A
In
DCLK
In
DCLK
Out
DCLK
Out
DCLK
In
DCLK
In
Async
In
Async
www.xilinx.com
Description
Differential complements
forming a differential receiver
input pair for each transceiver.
Differential complements
forming a differential
transmitter output pair for
each transceiver.
Description
Reference clock input to the shared
PMA PLL.
DRP address bus.
DRP interface clock.
Enables DRP read or write operations.
Data bus for writing configuration data
from the FPGA fabric to the
GTP_DUAL tile.
Data bus for reading configuration data
from the GTP_DUAL tile to the FPGA
fabric.
Indicates the operation is complete
for DRP write operations and data is
valid for DRP read operations.
Indicates whether the DRP operation is
a read or a write.
Starts the full GTP_DUAL reset
sequence.
Factory test pins. Must be strapped
Low for normal operation.
Virtex-5 RocketIO GTP Transceiver User Guide
R
Section (Page)
RX Termination and
Equalization
(page 125)
Configurable TX Driver
(page 113)
Section (Page)
Shared PMA PLL
(page 61),
Clocking
(page 70),
Power
Control
(page 81)
Dynamic
Reconfiguration Port
(DRP)
(page 87)
Dynamic
Reconfiguration Port
(DRP)
(page 87)
Dynamic
Reconfiguration Port
(DRP)
(page 87)
Dynamic
Reconfiguration Port
(DRP)
(page 87)
Dynamic
Reconfiguration Port
(DRP)
(page 87)
Dynamic
Reconfiguration Port
(DRP)
(page 87)
Dynamic
Reconfiguration Port
(DRP)
(page 87)
Reset
(page 73)
UG196 (v1.3) May 25, 2007
Advertisement
Table of Contents
