Xilinx Virtex-5 RocketIO GTP User Manual page 306

Appendix D: DRP Address Map of the GTP_DUAL Tile
Table D-11: DRP Addresses 40 through 47
Bit
40
SATA_MAX_ SATA_MAX_
0
WAKE_0[0] BURST_0[4]
SATA_MAX_ SATA_MAX_
1
WAKE_0[1] BURST_0[5]
SATA_MAX_ SATA_IDLE_
2
WAKE_0[2] VAL_0[0]
SATA_MAX_ SATA_IDLE_
3
WAKE_0[3] VAL_0[1]
SATA_MAX_ SATA_IDLE_
4
WAKE_0[4] VAL_0[2]
SATA_MAX_ SATA_BURST
5
WAKE_0[5] _VAL_0[0]
SATA_MAX_ SATA_BURST
6
INIT_0[0] _VAL_0[1]
SATA_MAX_ SATA_BURST
7
INIT_0[1] _VAL_0[2]
SATA_MAX_ RX_XCLK_
8
INIT_0[2]
SATA_MAX_ RX_STATUS_
9
INIT_0[3]
SATA_MAX_ RX_SLIDE_
10
INIT_0[4] MODE_0
RX_LOS_
SATA_MAX_
11 THRESHOLD
INIT_0[5]
RX_LOS_
SATA_MAX_
12 THRESHOLD
BURST_0[0]
RX_LOS_
SATA_MAX_
13 THRESHOLD
BURST_0[1]
RX_LOSS_OF
SATA_MAX_
14 _SYNC_FSM_
BURST_0[2]
RX_LOS_
SATA_MAX_
15 INVALID_
BURST_0[3]
INCR_0[0]
306
41 42
RX_LOS_ PRBS_ERR_
INVALID_ THRESHOLD
INCR_0[1]
RX_LOS_ PRBS_ERR_
INVALID_ THRESHOLD
INCR_0[2]
RX_DECODE PRBS_ERR_
_SEQ_ THRESHOLD
MATCH_0
PRBS_ERR_
RX_BUFFER_
THRESHOLD
USE_0
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[0]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[1]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[2]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[3]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
SEL_0
_0[4]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
FMT_0
_0[5]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[6]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[0] _0[7]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[1] _0[8]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[2] _0[9]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
0 _0[10]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_0[11]
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Address
43 44
PRBS_ERR_
PMA_CDR_
THRESHOLD
SCAN_0[12]
_0[12] _0[28]
PRBS_ERR_
PMA_CDR_
THRESHOLD
SCAN_0[13]
_0[13] _0[29]
PRBS_ERR_
PMA_CDR_
THRESHOLD
SCAN_0[14]
_0[14] _0[30]
PRBS_ERR_
PMA_CDR_
THRESHOLD
SCAN_0[15]
_0[15] _0[31]
PMA_CDR_ PMA_CDR_
SCAN_0[0] SCAN_0[16]
_0[16]
PMA_CDR_ PMA_CDR_
SCAN_0[1] SCAN_0[17]
_0[17]
PMA_CDR_ PMA_CDR_
SCAN_0[2] SCAN_0[18]
_0[18]
PMA_CDR_ PMA_CDR_
SCAN_0[3] SCAN_0[19]
_0[19]
PMA_CDR_ PMA_CDR_
SCAN_0[4] SCAN_0[20]
_0[20]
PMA_CDR_ PMA_CDR_
SCAN_0[5] SCAN_0[21]
_0[21]
PMA_CDR_ PMA_CDR_
SCAN_0[6] SCAN_0[22]
_0[22]
PMA_CDR_ PMA_CDR_
SCAN_0[7] SCAN_0[23]
_0[23]
PMA_CDR_ PMA_CDR_
SCAN_0[8] SCAN_0[24]
_0[24]
PMA_CDR_ PMA_CDR_
SCAN_0[9] SCAN_0[25]
_0[25]
PMA_CDR_ PMA_CDR_
SCAN_0[10] SCAN_0[26]
_0[26]
PMA_CDR_
TXDIVSEL_
SCAN_0[11]
_0[27] OUT_0[0]
Virtex-5 RocketIO GTP Transceiver User Guide
45 46
PLL_
TXDIVSEL_
OUT_0[1]
PLL_SATA_0 BOND_SEQ_2
PLL_
RXDIVSEL_ BOND_SEQ_2
OUT_0[0]
PLL_
RXDIVSEL_ BOND_SEQ_2
OUT_0[1]
PCOMMA_
BOND_SEQ_2
DETECT_0
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[0]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[1]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[2]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[3]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[4]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[5]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[6]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[7]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[8]
PCOMMA_
10B_VALUE_ BOND_SEQ_2
0[9]
PLL_
PCI_EXPRESS
BOND_SEQ_2
_MODE_0
UG196 (v1.3) May 25, 2007
R
47
Do Not
Modify
CHAN_
_3_0[8]
CHAN_
_3_0[7]
CHAN_
_3_0[6]
CHAN_
_3_0[5]
CHAN_
_3_0[4]
CHAN_
_3_0[3]
CHAN_
_3_0[2]
CHAN_
_3_0[1]
CHAN_
_3_0[0]
CHAN_
_4_0[9]
CHAN_
_4_0[8]
CHAN_
_4_0[7]
CHAN_
_4_0[6]
CHAN_
_4_0[5]
CHAN_
_4_0[4]