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Chapter 5: Tile Features
Table 5-10
Table 5-10: Power Attributes
Description
The GTP_DUAL tile offers different levels of power control. Each channel in each direction
can be powered down separately using TXPOWERDOWN and RXPOWERDOWN.
Additionally, the shared PMA PLL and the reference clock section can be powered down,
which affects both channels and both directions. The ports PLLPOWERDOWN and
REFCLKPWRDNB directly affect the shared PMA PLL and therefore both channels of the
GTP_DUAL tile.
Generic GTP Power Control Capabilities
The GTP_DUAL tile provides several power control features that can be used in a wide
variety of applications.
column describes how long after a power control mode is disabled that normal operation
can resume.
82
defines the power attributes.
Attribute
CLK25_DIVIDER
PCI_EXPRESS_MODE_0
PCI_EXPRESS_MODE_1
TRANS_TIME_FROM_P2_0
TRANS_TIME_FROM_P2_1
TRANS_TIME_NON_P2_0
TRANS_TIME_NON_P2_1
TRANS_TIME_TO_P2_0
TRANS_TIME_TO_P2_1
Table 5-11
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Description
The internal digital logic for GTP_DUAL tile management
runs at about 25 MHz. CLK25_DIVIDER is set to get an
internal clock for the tile. The CLK25_DIVIDER in
conjunction with CLKIN determines the timing of PCIe
powerdown state transitions by adjusting the internal
25 MHz clock rate.
Setting this attribute to TRUE enables certain operations
specific to PCI Express, specifically, recognizing
TXELECIDLE = 1, TXCHARDISPMODE = 1,
TXCHARDISPVAL = 0 as a request to power down the
channel.
TXCHARDISPMODE = 1 and TXCHARDISPVAL = 0 encode
the PIPE interface signal TXCompliance = 1 of the PIPE (the
latter two values being the encoding for PIPE and enabling
special support for FTS lane deskew).
Transition time from the P2 state in internal 25 MHz clock
cycles. The exact time depends on the CLKIN rate and the
setting of CLK25_DIVIDER. The P2 state is related to the PCI
Express power state definition.
Transition time to or from any state except P2 in internal
25 MHz clock cycles. The exact time depends on the CLKIN
rate and the setting of CLK25_DIVIDER. This setting is
related to the PCI Express power state definition.
Transition time to the P2 state in internal 25 MHz clock cycles.
The exact time depends on the CLKIN rate and the setting of
CLK25_DIVIDER. This setting is related to the PCI Express
power state definition.
summarizes these capabilities. The Recovery Time
Virtex-5 RocketIO GTP Transceiver User Guide
R
UG196 (v1.3) May 25, 2007
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