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Chapter 4: Implementation
XC5VLX50T: Not Available
XC5VLX85T: Not Available
XC5VLX110T: GTP_DUAL_X0Y7
XC5VSX50T: Not Available
XC5VSX95T: GTP_DUAL_X0Y7
XC5VLX50T: GTP_DUAL_X0Y5
XC5VLX85T: GTP_DUAL_X0Y5
XC5VLX110T: GTP_DUAL_X0Y6
XC5VSX50T: GTP_DUAL_X0Y5
XC5VSX95T: GTP_DUAL_X0Y6
XC5VLX50T: GTP_DUAL_X0Y4
XC5VLX85T: GTP_DUAL_X0Y4
XC5VLX110T: GTP_DUAL_X0Y5
XC5VSX50T: GTP_DUAL_X0Y4
XC5VSX95T: GTP_DUAL_X0Y5
XC5VLX50T: GTP_DUAL_X0Y3
XC5VLX85T: GTP_DUAL_X0Y3
XC5VLX110T: GTP_DUAL_X0Y4
XC5VSX50T: GTP_DUAL_X0Y3
XC5VSX95T: GTP_DUAL_X0Y4
Figure 4-3: XC5VLX50T-FF1136, XC5VLX85T-FF1136, XC5VLX110T-FF1136, XC5VSX50T-FF1136, and XC5VSX95T-FF1136 GTP Placement (1 of 2)
54
Right Edge of the Die
D8
C8
A6
A7
A9
A8
B5
B6
B10
B9
E4
D4
D1
C1
A3
A2
E2
D2
B4
B3
H4
H3
K1
J1
G1
H1
L2
K2
F2
G2
P4
P3
T1
R1
N1
P1
U2
T2
M2
N2
www.xilinx.com
MGTREFCLKP_124
C6
MGTREFCLKN_124
MGTRXP1_124
C7
MGTRXN1_124
D7
MGTRXP0_124
C9
MGTRXN0_124
MGTTXP1_124
C10 MGTAVTTTX_124
MGTTXN1_124
C5
MGTTXP0_124
MGTTXN0_124
MGTREFCLKP_120
D3
MGTREFCLKN_120
MGTRXP1_120
D5
MGTRXN1_120
F4
MGTRXP0_120
C3
MGTRXN0_120
MGTTXP1_120
C4
MGTTXN1_120
E3
MGTTXP0_120
MGTTXN0_120
MGTREFCLKP_116
K3
MGTREFCLKN_116
MGTRXP1_116
J3
MGTRXN1_116
J4
MGTRXP0_116
G3
MGTRXN0_116
MGTTXP1_116
F3
MGTTXN1_116
L3
MGTTXP0_116
MGTTXN0_116
MGTREFCLKP_112
T3
MGTREFCLKN_112
MGTRXP1_112
R3
MGTRXN1_112
R4
MGTRXP0_112
N3
MGTRXN0_112
MGTTXP1_112
U3
MGTTXN1_112
M3
MGTTXP0_112
MGTTXN0_112
Virtex-5 RocketIO GTP Transceiver User Guide
R
Power Pins
MGTAVCCPLL_124
MGTAVCC_124
MGTAVCC_124
MGTAVTTRX_124
MGTAVTTTX_124
MGTAVCCPLL_120
MGTAVCC_120
MGTAVCC_120
MGTAVTTRX_120
MGTAVTTTX_120
MGTAVTTTX_120
MGTAVCCPLL_116
MGTAVCC_116
MGTAVCC_116
MGTAVTTRX_116
MGTAVTTTX_116
MGTAVTTTX_116
MGTAVCCPLL_112
MGTAVCC_112
MGTAVCC_112
MGTAVTTRX_112
MGTAVTTTX_112
MGTAVTTTX_112
UG196_c4_03_012007
UG196 (v1.3) May 25, 2007
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