Xilinx Virtex-5 RocketIO GTP User Manual page 27

R
Table 1-3: GTP_DUAL Port Summary (Continued)
Port
RXCHBONDO0[2:0]
RXCHBONDO1[2:0]
RXCLKCORCNT0[2:0]
RXCLKCORCNT1[2:0]
RXCOMMADET0
RXCOMMADET1
RXCOMMADETUSE0
RXCOMMADETUSE1
RXDATA0
RXDATA1
RXDATAWIDTH0
RXDATAWIDTH1
RXDEC8B10BUSE0
RXDEC8B10BUSE1
RXDISPERR0[1:0]
RXDISPERR1[1:0]
RXELECIDLE0
RXELECIDLE1
RXELECIDLERESET0
RXELECIDLERESET1
RXENCHANSYNC0
RXENCHANSYNC1
RXENELECIDLERESETB
RXENEQB0
RXENEQB1
RXENMCOMMAALIGN0
RXENMCOMMAALIGN1
RXENPCOMMAALIGN0
RXENPCOMMAALIGN1
RXENPRBSTST0[1:0]
RXENPRBSTST1[1:0]
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Dir Domain
Out RXUSRCLK FPGA channel bonding control.
Reports the status of the elastic buffer
Out RXUSRCLK2
clock correction.
Asserted when the comma alignment
Out RXUSRCLK2
block detects a comma.
Activates the comma detection and
In RXUSRCLK2
alignment circuit.
Receive data bus of the receive interface
Out RXUSRCLK2
to the FPGA.
Selects the width of the RXDATA
In RXUSRCLK2
receive data connection to the FPGA.
In RXUSRCLK2 Enables the 8B/10B decoder.
Indicates if RXDATA was received with
Out RXUSRCLK2
a disparity error.
Indicates the differential voltage
Out RXUSRCLK2 between RXN and RXP dropped below
the minimum threshold.
Resets the RX Clock Data Recovery
In Async circuit, used by the mandatory link idle
reset circuit.
In RXUSRCLK2 Enables channel bonding.
Enables the RXELECIDLERESET
In Async inputs, used by the mandatory Link
Idle Reset circuit (active Low).
Enables receiver equalization (active
In Async
Low).
Aligns the byte boundary when comma
In RXUSRCLK2
minus is detected.
Aligns the byte boundary when comma
In RXUSRCLK2
plus is detected.
In RXUSRCLK2 Receiver test pattern checker control.
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Description
Ports and Attributes
Section (Page)
Configurable Channel
Bonding (Lane Deskew)
(page 176)
Configurable Clock
Correction (page 169)
Configurable Comma
Alignment and
Detection (page 150)
Configurable Comma
Alignment and
Detection (page 150)
FPGA RX Interface
(page 182)
FPGA RX Interface
(page 182)
Configurable 8B/10B
Decoder (page 157)
Configurable 8B/10B
Decoder (page 157)
RX OOB/Beacon
Signaling (page 130)
Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)
Configurable Channel
Bonding (Lane Deskew)
(page 176)
Reset (page 73), RX
Clock Data Recovery
(CDR) (page 136)
RX Termination and
Equalization (page 125)
Configurable Comma
Alignment and
Detection (page 150)
Configurable Comma
Alignment and
Detection (page 150)
PRBS Detection
(page 147)
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