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Chapter 5: Tile Features
Clocking using GREFCLK
The internal clock nets of the FPGA can provide the reference clock for the GTP_DUAL by
connecting the output of a global clock buffer (BUFG) or a regional clock buffer (BUFR) to
the CLKIN port. This type of clocking, called GREFCLK clocking, has the lowest
performance of any of the three clocking methods, because FPGA clocking resources
introduce too much jitter for operation at high rates. GREFCLK clocking should be
avoided, if possible. See the Virtex-5 Data Sheet for the jitter margins at different speeds.
Figure 5-6
it must be located in the same region as the GTP_DUAL tile.
Reset
Overview
The GTP_DUAL tile must be reset before any of the GTP transceivers can be used. There
are three ways to reset a GTP_DUAL tile:
1.
2.
3.
This section also includes the instructions for implementing the Link Idle Reset circuit.
This circuit must be implemented with all instances of the GTP_DUAL tile to allow the RX
CDR circuit to operate correctly.
72
shows how a GTP_DUAL tile connects to a BUFR or a BUFG. If a BUFR is used,
Notes:
1. Refer to the Virtex-5 Data Sheet and the Virtex-5 Configuration
Guide for the maximum clock frequency and jitter
limitations of BUFR.
Figure 5-6: Single GTP_DUAL Tile Clocked from the FPGA
Power up and configure the FPGA. Power-up reset is covered in this section.
Drive the GTPRESET port High to trigger a full asynchronous reset of the GTP_DUAL
tile. GTPRESET is covered in this section.
Assert one or more of the individual reset signals on the block to reset a specific
subcomponent of the tile. These resets are covered in detail in the sections for each
subcomponent.
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GTP_DUAL
BUFG or BUFR
CLKIN
UG196_c5_06_100606
Virtex-5 RocketIO GTP Transceiver User Guide
(1)
UG196 (v1.3) May 25, 2007
R
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