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Chapter 11: Design Constraints Overview
If more than one clock source is driving a single reference clock differential pair, a high-
speed switch should be used. When multiple clock sources are bused together on a single
connection, the signal integrity of the clock is not optimal due to the presence of stubs.
Using a high-speed switch makes every clock path point-to-point with one driver and one
receiver.
One example is when an unpopulated oscillator shares the same trace to the clock input
pin as another clock source. The trace segment from the pad to the junction is a stub. Any
signal travelling down the segment is reflected due to the different impedance presented
by the open end at the pad.
For applications where a single reference clock source must drive multiple inputs, high-
speed clock buffers should be used for clock distribution to eliminate stubs and reduce
reflections on the clock lines.
Coupling
DC Coupling
DC coupling can be used when the common mode ranges of the interconnecting devices
are the same. Any discrepancy in the common mode not only takes margin away from the
differential voltage swing but can also damage the device.
AC Coupling
AC coupling isolates the common modes of the two devices and is the preferred
configuration in hot-plug applications. The capacitor prevents any DC current from
flowing between connected devices.
Some transceivers have built-in DC blocking capacitors with programmable bypass. In
most cases, an external DC blocking capacitor is needed to provide adequate system-level
performance.
External Capacitor Value Selection
If an external DC blocking capacitor is needed, it is important to select an appropriate
value. The selection of a capacitor value is a trade-off between the following contradictory
criteria:
•
•
PDJ is not an issue in protocols using line codings that preserve DC balance. DC balance is
the property where the average number of 1s and 0s transmitted are equal. 8B/10B is an
example of a line-coding scheme that provides DC balance. When 8B/10B encoding is
used, 0.01 µF capacitors in a 0402 (EIA) package are suitable for external AC coupling at
3.125 Gb/s.
Line coding schemes that do not guarantee DC balance require more careful analysis. An
example includes SONET, which uses scrambling to ensure adequate symbol transitions
but does not provide DC balance. The remainder of this section provides the theory
needed to select a blocking capacitor value appropriate for the application.
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Encoding schemes with longer run lengths require larger capacitance values to reduce
pattern dependent jitter (PDJ).
Higher data rates require smaller capacitor values to reduce edge rate degradation.
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Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
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