Xilinx Virtex-5 RocketIO GTP User Manual page 22

Chapter 1: Introduction to the RocketIO GTP Transceiver
Figure 1-2
shared resources block. GTP_DUAL is the HDL primitive used to operate GTP
transceivers in the FPGA.
Package Pins
MGTTXP0 TXP0
MGTTXN0 TXN0
MGTRXP0 RXP0
MGTRXN0 RXN0
MGTAVTTTX AVTTTX
MGTAVTTRX AVTTRX
MGTAVTTTX AVTTTX
MGTAVCC AVCC
MGTAVCCPLL AVCCPLL
MGTAVCC AVCC
MGTTXP1 TXP1
MGTTXN1 TXN1
MGTRXP1 RXP1
MGTRXN1 RXN1
Notes:
1. CLKIN is a simplification for a clock source. See
22
shows a diagram of a GTP_DUAL tile, containing two GTP transceivers and a
GTP_DUAL
GTP0
GTP TX
TX-PMA TX-PCS
GTP RX
RX-PMA RX-PCS
Reset
Shared
Control
PMA
PLL
Power
PLL Lock
Control
Detection
GTP1
GTP TX
TX-PMA TX-PCS
RX-PMA RX-PCS
Figure 5-3, page 69
Figure 1-2: GTP_DUAL Tile Block Diagram
www.xilinx.com
Shared Resources
Clocking
DRP
for details on CLKIN.
Virtex-5 RocketIO GTP Transceiver User Guide
R
FPGA Pins
TXDATA0[15:0]
TXBYPASS8B10B0[1:0]
TXCHARISK0[1:0]
TXCHARDISPMODE0[1:0]
TXCHARDISPVAL0[1:0]
RXPOWERDOWN0[1:0]
RXSTATUS0[2:0]
RXDATA0[15:0]
RXNOTINTABLE0[1:0]
RXDISPERR0[1:0]
RXCHARISCOMMA0[1:0]
RXCHARISSK0[1:0]
RXRUNDISP0[1:0]
RXVALID0[1:0]
TXOUTCLK0
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
RXRECCLK0
(1)
CLKIN
TXOUTCLK1
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
RXRECCLK1
TXDATA1[15:0]
TXBYPASS8B10B1[1:0]
TXCHARISK1[1:0]
TXCHARDISPMODE1[1:0]
TXCHARDISPVAL1[1:0]
RXPOWERDOWN1[1:0]
RXSTATUS1[2:0]
RXDATA1[15:0]
RXNOTINTABLE1[1:0]
RXDISPERR1[1:0]
RXCHARISCOMMA1[1:0]
RXCHARISSK1[1:0]
RXRUNDISP1[1:0]
RXVALID1[1:0]
UG196_c1_02_041307
UG196 (v1.3) May 25, 2007