Xilinx Virtex-5 RocketIO GTP User Manual page 69

R
GTP_DUAL Tile
PLL
GTP_DUAL Tile
PLL
GTP_DUAL Tile
PLL
GTP_DUAL Tile
PLL
GTP_DUAL Tile
PLL
GTP_DUAL Tile
PLL
GTP_DUAL Tile
PLL
GTP_DUAL Tile
PLL
Note:
Refer to Chapter 10, "GTP-to-Board Interface" REFCLK Guidelines
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Clock
CLKIN
Muxing
CLKIN Clock
Muxing
Clock
CLKIN
Muxing
Clock
CLKIN
Muxing
Clock
CLKIN
Muxing
CLKIN
Clock
Muxing
CLKIN Clock
Muxing
Clock
CLKIN
Muxing
Figure 5-3: GTP Transceiver Clocking
www.xilinx.com
BUFG/
GTP
GREFCLK
BUFR
Dedicated
Clock
Routing
BUFG/
GTP
GREFCLK
BUFR
Dedicated
Clock
Routing
BUFG/
GTP
GREFCLK
BUFR
Dedicated
Clock
Routing
BUFG/
GTP
GREFCLK
BUFR
Dedicated
Clock
Routing
BUFG/
GREFCLK GTP
BUFR
Dedicated
Clock
Routing
BUFG/
GTP
GREFCLK
BUFR
Dedicated
Clock
Routing
BUFG/
GTP
GREFCLK
BUFR
Dedicated
Clock
Routing
BUFG/
GTP
GREFCLK
BUFR
Dedicated
Clock
Routing
for IBUFDS details.
Clocking
MGTREFCLKP
IBUFDS
MGTREFCLKN
MGTREFCLKP
IBUFDS
MGTREFCLKN
MGTREFCLKP
IBUFDS
MGTREFCLKN
MGTREFCLKP
IBUFDS
MGTREFCLKN
MGTREFCLKP
IBUFDS
MGTREFCLKN
MGTREFCLKP
IBUFDS
MGTREFCLKN
MGTREFCLKP
IBUFDS
MGTREFCLKN
MGTREFCLKP
IBUFDS
MGTREFCLKN
UG196_c5_03_110206
69