Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

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Ports and Attributes

Table 7-30
Table 7-30: Clock Correction Ports
Port
INTDATAWIDTH
RXBUFRESET0
RXBUFRESET1
RXBUFSTATUS0[2:0]
RXBUFSTATUS1[2:0]
RXCLKCORCNT0[2:0]
RXCLKCORCNT1[2:0]
Notes:
1. 10-bit internal data width is necessary when the RX buffer is bypassed.
2. If an RX buffer overflow or an RX buffer underflow condition occurs, the content of the RX buffer becomes invalid, and the RX
buffer needs re-initialization by asserting RXBUFRESET.
Table 7-31
Table 7-31: Clock Correction Attributes
Attribute
CLK_CORRECT_USE_0
CLK_CORRECT_USE_1
CLK_COR_ADJ_LEN_0
CLK_COR_ADJ_LEN_1
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
defines the clock correction ports.
Dir Clock Domain
Specifies the bit width for the TX and RX internal datapaths. This
port controls both transceivers on the tile:
In Async
In Async Resets the RX buffer logic and re-initializes the RX buffer.
Indicates the status of the RX buffer as follows:
Out RXUSRCLK2
Reports the clock correction status of the elastic buffer:
Out RXUSRCLK2
defines the clock correction attributes.
Enables clock correction.
FALSE: Clock correction disabled
TRUE: Clock correction enabled
This attribute defines the size of the adjustment (number of bytes repeated or
skipped) in a clock correction. The bytes skipped or repeated always start from
the beginning of the clock correction sequence to allow more bytes to be replaced
than in the specified clock correction sequence. Valid lengths are from one to four
bytes.
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Description
0: 8-bit width
(1)
1: 10-bit width
000: Nominal condition
001: Number of bytes in buffer is less than
CLK_COR_MIN_LAT
010: Number of bytes in buffer is greater than
CLK_COR_MAX_LAT
(2)
101: RX Buffer Overflow
110: RX Buffer Underflow
000: No clock correction
001: 1 sequence skipped
010: 2 sequences skipped
011: 3 sequences skipped
100: 4 sequences skipped
101: Reserved
110: 2 sequences added
111: 1 sequence added
Description
Configurable Clock Correction
(2)
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