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Chapter 7: GTP Receiver (RX)
Table 7-16
Table 7-16: RX DCDR Attributes
Description
Each GTP transceiver includes a built-in 5x digital oversampling circuit, which must be
used when operating the transceiver at line rates between 100 and 500 Mb/s.
Oversampling applies to both transceivers in a GTP_DUAL tile. If oversampling is
activated for one transceiver, it is activated for both.
Configuring the GTP transceiver to use oversampling requires the following steps:
•
•
•
The RocketIO GTP Wizard automatically configures the GTP_DUAL tile and makes the
oversampling ports available when generating a GTP wrapper with oversampling
enabled.
Configuring the 5x Line Rate
The SIPO in the RX PMA must provide the oversampling block with 10 bits per parallel
cycle, sampled at a rate five times faster than the desired line rate. The required line rate for
the PMA is given by
To achieve the required line rate, the RX divider for the transceiver must be set so that the
resulting required PLL clock rate is within the PLL operating range of 1.0 – 2.2 GHz.
Equation 7-5
In to Parallel Out (SIPO)," page 141
The shared PLL, which is discussed in detail in
produce the required PLL clock frequency.
frequency is related to the frequency of CLKIN (the reference clock to the tile).
Oversampling mode automatically uses a 10-bit internal datapath in the PMA, regardless
of the INTDATAWIDTH setting. The lowest possible ratio of PLL_CLKDIV_FB to
PLL_CLKDIV_REF is recommended.
144
defines the attributes for built-in digital oversampling.
Attribute
This shared attribute is also defined in
60
102. It applies to both sides of both GTP transceivers on the
OVERSAMPLE_MODE
GTP_DUAL tile.
When TRUE, 5X oversampling is On.
Configuring the 5x line rate
Configuring the PCS internal datapath and clocks
Activating and operating the oversampling block
Equation
PMALineRate
shows the relationship between the required rate and the PLL clock.
PMALineRate
f
=
------------------------------------------------------------------------------------------------------------ -
PLLClock
f
=
PLLClock
www.xilinx.com
Description
and
"TX Buffering, Phase Alignment, and Buffer Bypass," page
7-4.
×
=
5
DesiredLineRate
provides more information about the local RX divider.
×
PLL_RXDIVSEL_OUT
2
"Shared PMA PLL," page
Equation 7-6
×
5
PLL_CLKDIV_FB
×
---------------------------------------------------------- -
f
CLKIN
PLL_CLKDIV_REF
Virtex-5 RocketIO GTP Transceiver User Guide
"Shared PMA PLL," page
Equation 7-4
Equation 7-5
60, must be set to
shows how the PLL clock
Equation 7-6
UG196 (v1.3) May 25, 2007
R
"Serial
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