Configuring The Shared Pll For Gigabit Ethernet - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 5: Tile Features
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Configuring the Shared PLL for Gigabit Ethernet

This example shows how to set the shared PLL divider settings for Gigabit Ethernet using
Equation
example is provided only to illustrate the process with
Use
1.
2.
3.
4.
5.
6.
66
Calculate the required DIV value.
Because the internal datapath with must be eight bits and INTDATAWIDTH = 0,
DIV = 4.
Calculate the required PLL divider ratio
Using the values f , DIV, and f
CLKIN
Equation 5-1 to calculate the divider ratio as shown in
ratio of two.
PLL_DIVSEL_FB
---------------------------------------------------- -
PLL_DIVSEL_REF
Select the PLL divider values
Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 2 and PLL_DIVSEL_REF = 1 results in a ratio of two.
5-1. The RocketIO GTP Wizard and
Equation 5-1 as described in the following steps:
Determine the required line rates.
For Gigabit Ethernet, both TX and RX use a line rate of 1.25 Gb/s.
Determine the internal datapath width.
Because Gigabit Ethernet uses 8B/10B encoding, an internal datapath width of 10 bits
is required.
Determine the desired reference clock rate.
This example uses a reference clock running at 125 MHz.
Calculate the required PLL clock rate.
Because the SIPO block uses both edges of the clock to deserialize data, it must be fed
a clock running at 1.25/2 = 0.625 GHz. Because this RX rate of 0.625 GHz is below the
operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be two
to allow the PLL to run twice as fast (1.25 GHz). The PLL clock rate is thus 0.625 x 2 =
1.25 GHz.
Calculate the required DIV value.
Because the internal datapath with must be 10 bits and INTDATAWIDTH = 1, DIV = 5.
Calculate the required PLL divider ratio.
Using the values f , DIV, and f
CLKIN
Equation 5-1 to calculate the divider ratio as shown in
ratio of two.
PLL_DIVSEL_FB
---------------------------------------------------- -
PLL_DIVSEL_REF
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determined above, rearrange
PLL_CLOCK
f
1.244 GHz
PLL_Clock
---------------------------------- - ------------------------------------- -
= =
×
f DIV 155.5 MHz
CLKIN
Table 5-3 are simpler alternatives. This
Equation
determined above, rearrange
PLL_CLOCK
f
1.25 GHz
PLL_Clock
----------------------------------- --------------------------------- -
= =
×
f DIV 125 MHz
CLKIN
Virtex-5 RocketIO GTP Transceiver User Guide
Equation 5-3. The result is a
2 Equation 5-3
=
×
4
5-1.
Equation 5-4. The result is a
= 2 Equation 5-4
×
5
UG196 (v1.3) May 25, 2007
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